[llvm] c74acd8 - X86ISelLowering.cpp - clang-format to fix col80 limit. NFC.

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Tue Apr 21 07:18:40 PDT 2020


Author: Simon Pilgrim
Date: 2020-04-21T15:18:23+01:00
New Revision: c74acd8fc99afdf35513964fca52efa6dac08b30

URL: https://github.com/llvm/llvm-project/commit/c74acd8fc99afdf35513964fca52efa6dac08b30
DIFF: https://github.com/llvm/llvm-project/commit/c74acd8fc99afdf35513964fca52efa6dac08b30.diff

LOG: X86ISelLowering.cpp - clang-format to fix col80 limit. NFC.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d6debce941e5..8457bce9a04b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -47304,9 +47304,11 @@ static SDValue combineExtInVec(SDNode *N, SelectionDAG &DAG,
     auto *Ld = cast<LoadSDNode>(In);
     if (Ld->isSimple()) {
       MVT SVT = In.getSimpleValueType().getVectorElementType();
-      ISD::LoadExtType Ext = N->getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
-      EVT MemVT = EVT::getVectorVT(*DAG.getContext(), SVT,
-                                   VT.getVectorNumElements());
+      ISD::LoadExtType Ext = N->getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG
+                                 ? ISD::SEXTLOAD
+                                 : ISD::ZEXTLOAD;
+      EVT MemVT =
+          EVT::getVectorVT(*DAG.getContext(), SVT, VT.getVectorNumElements());
       if (TLI.isLoadExtLegal(Ext, VT, MemVT)) {
         SDValue Load =
             DAG.getExtLoad(Ext, SDLoc(N), VT, Ld->getChain(), Ld->getBasePtr(),


        


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