[PATCH] D78480: [SelectionDAG] Fix legalization of non-byte-sized vector

[LemonBoy via Phabricator via llvm-commits]

LemonBoy created this revision.
LemonBoy added reviewers: bogner, craig.topper.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.

This is more a RFC than a patch submission at the moment.

`VectorLegalizer::ExpandLoad` contains some logic to legalize vectors whose element are not byte-sized by chopping them into their elements using bitwise ops and then build a legal vector out of the extracted elements.

The problem that I noticed in the attached test case is that with a `v4i5` vector the generated code (at least for X86) was incorrect: when trying to extract the third element (at offset 15) `ExpandLoad` doesn't keep track of the load sizes it uses (the `v4i5` is three-byte wide and so it's loaded as a i16 + i8`) and so it ends up extracting the msb plus 15 zeros out of the zero-extended i16 it loaded, discarding the top 4 bits stored in the nearby i8.

Instead of patching `ExpandLoad` I've just made it call `scalarizeVectorLoad` as that already contains the logic needed to "chop" the vector and without this problem.

(I actually had to add an `ISD::AND` in `scalarizeVectorLoad` as a single truncation is not always enough, if you consider something like `(anyext i64 (truncate i4 X))` that's simplified as `(i64 X)`)

The downside is that the X86 codegen is greatly worse in some cases as many opportunities to use vector ops are missed, I'm submitting this patch to ask if you think this is the right way to go and/or have any clue about the hugely different codegen.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78480

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/X86/avx512-extract-subvector-load-store.ll
  llvm/test/CodeGen/X86/bitcast-vector-bool.ll
  llvm/test/CodeGen/X86/clear_upper_vector_element_bits.ll
  llvm/test/CodeGen/X86/load-local-v3i1.ll
  llvm/test/CodeGen/X86/load-local-v4i5.ll
  llvm/test/CodeGen/X86/pr15267.ll
  llvm/test/CodeGen/X86/vector-sext.ll
  llvm/test/CodeGen/X86/vector-zext.ll

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