[PATCH] D78471: [x86/SLH] Pin function address in physical register after it been hardened.

[Pengfei Wang via Phabricator via llvm-commits]

pengfei created this revision.
pengfei added reviewers: chandlerc, echristo, rnk, craig.topper.
Herald added subscribers: llvm-commits, hiraditya, qcolombet, MatzeB.
Herald added a project: LLVM.

When physical registers are used in high pressure, there's a chance the
register used for speculative load hardening been spilt. To protect the
hardening not been corrupted, we need always pin it in physical
register.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78471

Files:
  llvm/lib/CodeGen/LiveIntervals.cpp
  llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll


Index: llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -x86-speculative-load-hardening | FileCheck %s
+
+define i32 @foo(void ()** %0) {
+; CHECK-LABEL: foo:
+; CHECK:         callq *%rax
+; CHECK-NEXT:  .Lslh_ret_addr0:
+; CHECK-NEXT:    movq %rsp, %rcx
+; CHECK-NEXT:    movq -{{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT:    sarq $63, %rcx
+; CHECK-NEXT:    cmpq $.Lslh_ret_addr0, %rax
+  %2 = load void ()*, void ()** %0
+  call void asm sideeffect "", "~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{dirflag},~{fpsr},~{flags}"()
+  call void %2()
+  ret i32 0
+}
Index: llvm/lib/CodeGen/LiveIntervals.cpp
===================================================================
--- llvm/lib/CodeGen/LiveIntervals.cpp
+++ llvm/lib/CodeGen/LiveIntervals.cpp
@@ -862,6 +862,11 @@
 float LiveIntervals::getSpillWeight(bool isDef, bool isUse,
                                     const MachineBlockFrequencyInfo *MBFI,
                                     const MachineInstr &MI) {
+  // FIXME: Is there place to add the check better than here?
+  // The pass x86-slh attached an post instruction symbol to call instruction.
+  // We don't want its register been spilt out.
+  if (MI.isCall() && MI.getPostInstrSymbol())
+    return huge_valf;
   return getSpillWeight(isDef, isUse, MBFI, MI.getParent());
 }
 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D78471.258653.patch
Type: text/x-patch
Size: 1571 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200420/24ea6cfa/attachment.bin>