[PATCH] D78312: [AMDGPU] Add 192-bit register classes

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:799
 
+def VReg_192 : RegisterClass<"AMDGPU", [untyped], 32, (add VGPR_192)> {
+  let Size = 192;
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I wander if we should just use for loop to define all the classes at once.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78312/new/

https://reviews.llvm.org/D78312