[PATCH] D78272: [PowerPC] DAG Combine to transform shifts into multiply-high
    Amy Kwan via Phabricator via llvm-commits 
    llvm-commits at lists.llvm.org
       
    Thu Apr 16 21:38:22 PDT 2020
    
    
  
amyk marked an inline comment as done.
amyk added inline comments.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:15918
+  // performed by the type legalizer.
+  if (Subtarget.isPPC64() && DCI.isBeforeLegalize())
+    if (SDValue MULH = combineShifttoMULH(N, DCI.DAG, *this, Subtarget))
----------------
lebedev.ri wrote:
> This doesn't look like the best check for this.
> Do we not want this transform in general, is it expected to be pessimizing somewhere?
> Then i'd expect it to be a TLI hook.
I actually realize now after doing some testing that it may be better to remove this check and to run this transformation in other passes, as well. I will update the patch to reflect this. Thanks for reviewing. 
Repository:
  rG LLVM Github Monorepo
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  https://reviews.llvm.org/D78272/new/
https://reviews.llvm.org/D78272
    
    
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