[PATCH] D78312: [AMDGPU] Add 192-bit register classes

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:1371
+    &AMDGPU::SReg_192RegClass,
     &AMDGPU::VReg_256RegClass,
     &AMDGPU::SReg_256RegClass,
----------------
Should also AReg_192


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:1546
+      AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
+      AMDGPU::sub4, AMDGPU::sub5,
+    };
----------------
Trailing comma


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78312/new/

https://reviews.llvm.org/D78312