[llvm] e68f1f2 - [SVE] Remove calls to getBitWidth from Hexagon

[Christopher Tetreault via llvm-commits]

Author: Christopher Tetreault
Date: 2020-04-14T11:09:49-07:00
New Revision: e68f1f2d4301a0f2c6dd5fdf90e4579e68499f3f

URL: https://github.com/llvm/llvm-project/commit/e68f1f2d4301a0f2c6dd5fdf90e4579e68499f3f
DIFF: https://github.com/llvm/llvm-project/commit/e68f1f2d4301a0f2c6dd5fdf90e4579e68499f3f.diff

LOG: [SVE] Remove calls to getBitWidth from Hexagon

Reviewers: efriedma, sdesmalen, kparzysz

Reviewed By: kparzysz

Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77899

Added: 
    

Modified: 
    llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
index 4485b70c6eb5..bbc1a743c9cd 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
@@ -165,7 +165,7 @@ unsigned HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
 
   if (Src->isVectorTy()) {
     VectorType *VecTy = cast<VectorType>(Src);
-    unsigned VecWidth = VecTy->getBitWidth();
+    unsigned VecWidth = VecTy->getPrimitiveSizeInBits().getFixedSize();
     if (useHVX() && isTypeForHVX(VecTy)) {
       unsigned RegWidth = getRegisterBitWidth(true);
       assert(RegWidth && "Non-zero vector register width expected");