[PATCH] D76212: [X86] Make v32i16/v64i8 legal types without avx512bw. Use custom splitting instead.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:19833
 
-    In = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op),
-                     MVT::v16i8, In, DAG.getUNDEF(MVT::v8i8));
-    return DAG.getNode(ExtendInVecOpc, dl, VT, In);
+    return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
   }
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craig.topper wrote:
> RKSimon wrote:
> > Maybe update LowerVectorIntUnary so we can use it here? We just need to relax the requirement that the src/dst vector element types are equal which doesn't seem to really necessary.
> I think that requires us to pass the desired result VT to it so we need to update all call sites. I'm happy to do that, but wanted to make sure that's what you want.
Yeah, for *_EXTEND_VECTOR_INREG cases thats going to a pain - lets not bother.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:20395
+      Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::v16i8, Hi);
+      return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
+    }
----------------
For this case we know the #elements will match - its just the dst/src element types that differ, so a more minor adjustment to LowerVectorIntUnary should still work?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76212/new/

https://reviews.llvm.org/D76212