[PATCH] D78088: [MIR] Add comments to INLINEASM immediate flag MachineOperands

[Konstantin Schwarz via Phabricator via llvm-commits]

kschwarz created this revision.
kschwarz added reviewers: eli.friedman, SjoerdMeijer, arsenm.
kschwarz added a project: LLVM.
Herald added subscribers: kerbowa, atanasyan, jrtc27, hiraditya, nhaehnle, wdng, jvesely, sdardis, qcolombet.
kschwarz added a comment.
kschwarz edited reviewers, added: efriedma; removed: eli.friedman.

I've thought about adding enum to string conversion functions to InlineAsm.h, which could be reused from both MachineInstr.cpp and TargetInstrInfo.cpp to avoid code duplication.
Would that be preferred here?


The INLINEASM MIR instructions use immediate operands to encode the values of some operands.
The MachineInstr pretty printer function already handles those operands and prints human readable annotations instead of the immediates. This patch adds similar annotations to the output of the MIRPrinter, however uses the new MIROperandComment feature.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78088

Files:
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/lib/CodeGen/MIRPrinter.cpp
  llvm/lib/CodeGen/TargetInstrInfo.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.h
  llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
  llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
  llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
  llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
  llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
  llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
  llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
  llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
  llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
  llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
  llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
  llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
  llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
  llvm/test/CodeGen/Thumb2/high-reg-spill.mir
  llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
  llvm/test/CodeGen/X86/inline-asm-default-clobbers.ll
  llvm/test/CodeGen/X86/stack-folding-adx.mir
  llvm/test/CodeGen/X86/stack-folding-bmi2.mir
  llvm/test/CodeGen/X86/stack-folding-fp-nofpexcept.mir

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