[PATCH] D78070: [llvm][ADT] Move TypeSwitch class from MLIR to LLVM

[River Riddle via Phabricator via llvm-commits]

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This class implements a switch-like dispatch statement for a value of 'T' using dyn_cast functionality. Each `Case<T>` takes a callable to be invoked if the root value isa<T>, the callable is invoked with the result of dyn_cast<T>() as a parameter.

Depends On D78067 <https://reviews.llvm.org/D78067>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78070

Files:
  flang/lib/Optimizer/Dialect/FIROps.cpp
  flang/lib/Optimizer/Dialect/FIRType.cpp
  llvm/include/llvm/ADT/TypeSwitch.h
  llvm/unittests/ADT/CMakeLists.txt
  llvm/unittests/ADT/TypeSwitchTest.cpp
  mlir/examples/toy/Ch1/parser/AST.cpp
  mlir/examples/toy/Ch2/parser/AST.cpp
  mlir/examples/toy/Ch3/parser/AST.cpp
  mlir/examples/toy/Ch4/parser/AST.cpp
  mlir/examples/toy/Ch5/parser/AST.cpp
  mlir/examples/toy/Ch6/parser/AST.cpp
  mlir/examples/toy/Ch7/parser/AST.cpp
  mlir/include/mlir/ADT/TypeSwitch.h
  mlir/include/mlir/Support/LLVM.h
  mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
  mlir/lib/Dialect/SPIRV/Serialization/Serializer.cpp
  mlir/lib/TableGen/Operator.cpp
  mlir/lib/TableGen/Successor.cpp
  mlir/lib/TableGen/Type.cpp
  mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
  mlir/lib/Transforms/Utils/Utils.cpp
  mlir/test/lib/Transforms/TestMemRefBoundCheck.cpp
  mlir/tools/mlir-tblgen/OpFormatGen.cpp
  mlir/unittests/ADT/CMakeLists.txt
  mlir/unittests/ADT/TypeSwitchTest.cpp
  mlir/unittests/CMakeLists.txt

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