[llvm] f71350f - Add -debugify-and-strip-all to add debug info before a pass and remove it after
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 10 16:36:25 PDT 2020
Author: Daniel Sanders
Date: 2020-04-10T16:36:07-07:00
New Revision: f71350f05ae125b8b343b3a3a441537e353af039
URL: https://github.com/llvm/llvm-project/commit/f71350f05ae125b8b343b3a3a441537e353af039
DIFF: https://github.com/llvm/llvm-project/commit/f71350f05ae125b8b343b3a3a441537e353af039.diff
LOG: Add -debugify-and-strip-all to add debug info before a pass and remove it after
Summary:
This allows us to test each backend pass under the presence
of debug info using pre-existing tests. The tests should not
fail as a result of this so long as it's true that debug info
does not affect CodeGen.
In practice, a few tests are sensitive to this:
* Tests that check the pass structure (e.g. O0-pipeline.ll)
* Tests that check --debug output. Specifically instruction
dumps containing MMO's (e.g. prelegalizercombiner-extends.ll)
* Tests that contain debugify metadata as mir-strip-debug will
remove it (e.g. fastisel-debugvalue-undef.ll)
* Tests with partial debug info (e.g.
patchable-function-entry-empty.mir had debug info but no
!llvm.dbg.cu)
* Tests that check optimization remarks overly strictly (e.g.
prologue-epilogue-remarks.mir)
* Tests that would inject the pass in an unsafe region (e.g.
seqpairspill.mir would inject between register alloc and
virt reg rewriter)
In all cases, the checks can either be updated or
--debugify-and-strip-all-safe=0 can be used to avoid being
affected by something like llvm-lit -Dllc='llc --debugify-and-strip-all-safe'
I tested this without the lost debug locations verifier to
confirm that AArch64 behaviour is unaffected (with the fixes
in this patch) and with it to confirm it finds the problems
without the additional RUN lines we had before.
Depends on D77886, D77887, D77747
Reviewers: aprantl, vsk, bogner
Subscribers: qcolombet, kristof.beyls, hiraditya, danielkiss, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D77888
Added:
Modified:
llvm/include/llvm/CodeGen/TargetPassConfig.h
llvm/lib/CodeGen/MachineDebugify.cpp
llvm/lib/CodeGen/MachineStripDebug.cpp
llvm/lib/CodeGen/TargetPassConfig.cpp
llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
llvm/test/CodeGen/AArch64/O0-pipeline.ll
llvm/test/CodeGen/AArch64/O3-pipeline.ll
llvm/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll
llvm/test/CodeGen/AArch64/fastisel-debugvalue-undef.ll
llvm/test/CodeGen/AArch64/patchable-function-entry-empty.mir
llvm/test/CodeGen/AArch64/prologue-epilogue-remarks.mir
llvm/test/CodeGen/AArch64/seqpairspill.mir
llvm/test/CodeGen/AArch64/stp-opt-with-renaming-debug.mir
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetPassConfig.h b/llvm/include/llvm/CodeGen/TargetPassConfig.h
index f84e85c5c8f9..3a4c09163f32 100644
--- a/llvm/include/llvm/CodeGen/TargetPassConfig.h
+++ b/llvm/include/llvm/CodeGen/TargetPassConfig.h
@@ -103,6 +103,7 @@ class TargetPassConfig : public ImmutablePass {
bool Started = true;
bool Stopped = false;
bool AddingMachinePasses = false;
+ bool DebugifyIsSafe = true;
/// Set the StartAfter, StartBefore and StopAfter passes to allow running only
/// a portion of the normal code-gen pass sequence.
@@ -306,14 +307,20 @@ class TargetPassConfig : public ImmutablePass {
/// verification is enabled.
void addVerifyPass(const std::string &Banner);
+ /// Add a pass to add synthesized debug info to the MIR.
+ void addDebugifyPass();
+
+ /// Add a pass to remove debug info from the MIR.
+ void addStripDebugPass();
+
/// Add standard passes before a pass that's about to be added. For example,
/// the DebugifyMachineModulePass if it is enabled.
- void addMachinePrePasses();
+ void addMachinePrePasses(bool AllowDebugify = true);
/// Add standard passes after a pass that has just been added. For example,
/// the MachineVerifier if it is enabled.
void addMachinePostPasses(const std::string &Banner, bool AllowPrint = true,
- bool AllowVerify = true);
+ bool AllowVerify = true, bool AllowStrip = true);
/// Check whether or not GlobalISel should abort on error.
/// When this is disabled, GlobalISel will fall back on SDISel instead of
diff --git a/llvm/lib/CodeGen/MachineDebugify.cpp b/llvm/lib/CodeGen/MachineDebugify.cpp
index 86834dbc53d5..bee9b6346757 100644
--- a/llvm/lib/CodeGen/MachineDebugify.cpp
+++ b/llvm/lib/CodeGen/MachineDebugify.cpp
@@ -66,6 +66,7 @@ struct DebugifyMachineModule : public ModulePass {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineModuleInfoWrapperPass>();
AU.addPreserved<MachineModuleInfoWrapperPass>();
+ AU.setPreservesCFG();
}
static char ID; // Pass identification.
@@ -79,6 +80,6 @@ INITIALIZE_PASS_BEGIN(DebugifyMachineModule, DEBUG_TYPE,
INITIALIZE_PASS_END(DebugifyMachineModule, DEBUG_TYPE,
"Machine Debugify Module", false, false)
-ModulePass *createDebugifyMachineModulePass() {
+ModulePass *llvm::createDebugifyMachineModulePass() {
return new DebugifyMachineModule();
}
diff --git a/llvm/lib/CodeGen/MachineStripDebug.cpp b/llvm/lib/CodeGen/MachineStripDebug.cpp
index aeb2789c28c1..240d657b6b2d 100644
--- a/llvm/lib/CodeGen/MachineStripDebug.cpp
+++ b/llvm/lib/CodeGen/MachineStripDebug.cpp
@@ -111,6 +111,7 @@ struct StripDebugMachineModule : public ModulePass {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineModuleInfoWrapperPass>();
AU.addPreserved<MachineModuleInfoWrapperPass>();
+ AU.setPreservesCFG();
}
static char ID; // Pass identification.
@@ -127,6 +128,6 @@ INITIALIZE_PASS_BEGIN(StripDebugMachineModule, DEBUG_TYPE,
INITIALIZE_PASS_END(StripDebugMachineModule, DEBUG_TYPE,
"Machine Strip Debug Module", false, false)
-ModulePass *createStripDebugMachineModulePass(bool OnlyDebugified) {
+ModulePass *llvm::createStripDebugMachineModulePass(bool OnlyDebugified) {
return new StripDebugMachineModule(OnlyDebugified);
}
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp
index 448a08728e3f..336b1a883cf2 100644
--- a/llvm/lib/CodeGen/TargetPassConfig.cpp
+++ b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -114,6 +114,12 @@ static cl::opt<cl::boolOrDefault>
VerifyMachineCode("verify-machineinstrs", cl::Hidden,
cl::desc("Verify generated machine code"),
cl::ZeroOrMore);
+static cl::opt<cl::boolOrDefault> DebugifyAndStripAll(
+ "debugify-and-strip-all-safe", cl::Hidden,
+ cl::desc(
+ "Debugify MIR before and Strip debug after "
+ "each pass except those known to be unsafe when debug info is present"),
+ cl::ZeroOrMore);
enum RunOutliner { AlwaysOutline, NeverOutline, TargetDefault };
// Enable or disable the MachineOutliner.
static cl::opt<RunOutliner> EnableMachineOutliner(
@@ -605,10 +611,24 @@ void TargetPassConfig::addVerifyPass(const std::string &Banner) {
PM->add(createMachineVerifierPass(Banner));
}
-void TargetPassConfig::addMachinePrePasses() {}
+void TargetPassConfig::addDebugifyPass() {
+ PM->add(createDebugifyMachineModulePass());
+}
+
+void TargetPassConfig::addStripDebugPass() {
+ PM->add(createStripDebugMachineModulePass(/*OnlyDebugified=*/true));
+}
+
+void TargetPassConfig::addMachinePrePasses(bool AllowDebugify) {
+ if (AllowDebugify && DebugifyAndStripAll == cl::BOU_TRUE && DebugifyIsSafe)
+ addDebugifyPass();
+}
void TargetPassConfig::addMachinePostPasses(const std::string &Banner,
- bool AllowPrint, bool AllowVerify) {
+ bool AllowPrint, bool AllowVerify,
+ bool AllowStrip) {
+ if (DebugifyAndStripAll == cl::BOU_TRUE && DebugifyIsSafe)
+ addStripDebugPass();
if (AllowPrint)
addPrintPass(Banner);
if (AllowVerify)
@@ -794,6 +814,19 @@ bool TargetPassConfig::addCoreISelPasses() {
TM->setGlobalISel(true);
}
+ // FIXME: Injecting into the DAGISel pipeline seems to cause issues with
+ // analyses needing to be re-run. This can result in being unable to
+ // schedule passes (particularly with 'Function Alias Analysis
+ // Results'). It's not entirely clear why but AFAICT this seems to be
+ // due to one FunctionPassManager not being able to use analyses from a
+ // previous one. As we're injecting a ModulePass we break the usual
+ // pass manager into two. GlobalISel with the fallback path disabled
+ // and -run-pass seem to be unaffected. The majority of GlobalISel
+ // testing uses -run-pass so this probably isn't too bad.
+ SaveAndRestore<bool> SavedDebugifyIsSafe(DebugifyIsSafe);
+ if (Selector != SelectorType::GlobalISel || !isGlobalISelAbortEnabled())
+ DebugifyIsSafe = false;
+
// Add instruction selector passes.
if (Selector == SelectorType::GlobalISel) {
SaveAndRestore<bool> SavedAddingMachinePasses(AddingMachinePasses, true);
@@ -910,6 +943,11 @@ void TargetPassConfig::addMachinePasses() {
// Run pre-ra passes.
addPreRegAlloc();
+ // Debugifying the register allocator passes seems to provoke some
+ // non-determinism that affects CodeGen and there doesn't seem to be a point
+ // where it becomes safe again so stop debugifying here.
+ DebugifyIsSafe = false;
+
// Run register allocation and passes that are tightly coupled with it,
// including phi elimination and scheduling.
if (getOptimizeRegAlloc())
@@ -1124,6 +1162,7 @@ bool TargetPassConfig::addRegAssignmentOptimized() {
// Finally rewrite virtual registers.
addPass(&VirtRegRewriterID);
+
// Perform stack slot coloring and post-ra machine LICM.
//
// FIXME: Re-enable coloring with register when it's capable of adding
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll b/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
index f7cc409ea9d7..fba596d4e056 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
@@ -1,43 +1,54 @@
; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
+; RUN: --debugify-and-strip-all-safe=0 \
; RUN: -verify-machineinstrs=0 -O0 \
; RUN: | FileCheck %s --check-prefixes=ENABLED,ENABLED-O0,FALLBACK
; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
+; RUN: --debugify-and-strip-all-safe=0 \
; RUN: -verify-machineinstrs -O0 \
; RUN: | FileCheck %s --check-prefixes=ENABLED,ENABLED-O0,FALLBACK,VERIFY,VERIFY-O0
; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
+; RUN: --debugify-and-strip-all-safe=0 \
; RUN: -verify-machineinstrs=0 -O0 -aarch64-enable-global-isel-at-O=0 -global-isel-abort=1 \
; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix ENABLED-O0 --check-prefix NOFALLBACK
; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
+; RUN: --debugify-and-strip-all-safe=0 \
; RUN: -verify-machineinstrs=0 -O0 -aarch64-enable-global-isel-at-O=0 -global-isel-abort=2 \
; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix ENABLED-O0 --check-prefix FALLBACK
; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
+; RUN: --debugify-and-strip-all-safe=0 \
; RUN: -verify-machineinstrs=0 -global-isel \
; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix NOFALLBACK --check-prefix ENABLED-O1
; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
+; RUN: --debugify-and-strip-all-safe=0 \
; RUN: -verify-machineinstrs=0 -global-isel -global-isel-abort=2 \
; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix FALLBACK --check-prefix ENABLED-O1
; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
+; RUN: --debugify-and-strip-all-safe=0 \
; RUN: -verify-machineinstrs=0 -O1 -aarch64-enable-global-isel-at-O=3 \
; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix ENABLED-O1
; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
+; RUN: --debugify-and-strip-all-safe=0 \
; RUN: -verify-machineinstrs=0 -O1 -aarch64-enable-global-isel-at-O=0 \
; RUN: | FileCheck %s --check-prefix DISABLED
; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
+; RUN: --debugify-and-strip-all-safe=0 \
; RUN: -verify-machineinstrs=0 -aarch64-enable-global-isel-at-O=-1 \
; RUN: | FileCheck %s --check-prefix DISABLED
; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
+; RUN: --debugify-and-strip-all-safe=0 \
; RUN: -verify-machineinstrs=0 | FileCheck %s --check-prefix DISABLED
; RUN: llc -mtriple=aarch64-- -fast-isel=0 -global-isel=false \
+; RUN: --debugify-and-strip-all-safe=0 \
; RUN: -debug-pass=Structure %s -o /dev/null 2>&1 -verify-machineinstrs=0 \
; RUN: | FileCheck %s --check-prefix DISABLED
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
index 9128cb88c6b6..63e80af680d6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
@@ -112,15 +112,15 @@ body: |
# a test of the debug output and a test.
#
# CHECK-WORKLIST-LABEL: Generic MI Combiner for: multiple_copies
-# CHECK-WORKLIST: Try combining [[IN0:%[0-9]+]]:_(s8) = G_LOAD [[IN1:%[0-9]+]]:_(p0) :: (load 1 from %ir.addr)
+# CHECK-WORKLIST: Try combining [[IN0:%[0-9]+]]:_(s8) = G_LOAD [[IN1:%[0-9]+]]:_(p0){{.*}} :: (load 1 from %ir.addr)
# CHECK-WORKLIST: Preferred use is: [[IN2:%[0-9]+]]:_(s32) = G_SEXT [[IN0]]:_(s8)
-# CHECK-WORKLIST-DAG: Changing: [[IN0]]:_(s8) = G_LOAD [[IN1]]:_(p0) :: (load 1 from %ir.addr)
+# CHECK-WORKLIST-DAG: Changing: [[IN0]]:_(s8) = G_LOAD [[IN1]]:_(p0){{.*}} :: (load 1 from %ir.addr)
# CHECK-WORKLIST-DAG: Changing: [[IN3:%[0-9]+]]:_(s8) = G_ADD [[IN0]]:_, [[IN4:%[0-9]+]]:_
# CHECK-WORKLIST-DAG: Changed: [[IN3]]:_(s8) = G_ADD [[NEW1:%[0-9]+]]:_, [[IN4]]:_
# CHECK-WORKLIST-DAG: Changing: [[IN5:%[0-9]+]]:_(s8) = G_SUB [[IN0]]:_, [[IN6:%[0-9]+]]:_
# CHECK-WORKLIST-DAG: Changed: [[IN5]]:_(s8) = G_SUB [[NEW2:%[0-9]+]]:_, [[IN6]]:_
# CHECK-WORKLIST-DAG: Erasing: [[IN2]]:_(s32) = G_SEXT [[IN0]]:_(s8)
-# CHECK-WORKLIST-DAG: Changed: [[IN2]]:_(s32) = G_SEXTLOAD [[IN1]]:_(p0) :: (load 1 from %ir.addr)
+# CHECK-WORKLIST-DAG: Changed: [[IN2]]:_(s32) = G_SEXTLOAD [[IN1]]:_(p0){{.*}} :: (load 1 from %ir.addr)
# CHECK-WORKLIST-DAG: Created: [[NEW1]]:_(s8) = G_TRUNC [[IN2]]:_(s32)
# CHECK-WORKLIST-DAG: Created: [[NEW2]]:_(s8) = G_TRUNC [[IN2]]:_(s32)
# CHECK-WORKLIST: Try combining
@@ -211,9 +211,9 @@ body: |
$w0 = COPY %10
$w1 = COPY %11
# CHECK-WORKLIST-LABEL: Generic MI Combiner for: sink_to_phi_nondominating
-# CHECK-WORKLIST: Try combining [[IN0:%[0-9]+]]:_(s8) = G_LOAD [[IN1:%[0-9]+]]:_(p0) :: (load 1 from %ir.addr)
+# CHECK-WORKLIST: Try combining [[IN0:%[0-9]+]]:_(s8) = G_LOAD [[IN1:%[0-9]+]]:_(p0){{.*}} :: (load 1 from %ir.addr)
# CHECK-WORKLIST: Preferred use is: [[IN2:%[0-9]+]]:_(s32) = G_SEXT [[IN0]]:_(s8)
-# CHECK-WORKLIST-DAG: Changing: [[IN0]]:_(s8) = G_LOAD [[IN1]]:_(p0) :: (load 1 from %ir.addr)
+# CHECK-WORKLIST-DAG: Changing: [[IN0]]:_(s8) = G_LOAD [[IN1]]:_(p0){{.*}} :: (load 1 from %ir.addr)
# CHECK-WORKLIST-DAG: Creating: G_TRUNC
# CHECK-WORKLIST-DAG: Changing: [[IN3:%[0-9]+]]:_(s8) = G_ADD [[IN0]]:_, [[IN4:%[0-9]+]]:_
# CHECK-WORKLIST-DAG: Changed: [[IN3]]:_(s8) = G_ADD [[OUT1:%[0-9]+]]:_, [[IN4]]:_
@@ -221,7 +221,7 @@ body: |
# CHECK-WORKLIST-DAG: Changing: [[IN5:%[0-9]+]]:_(s8) = G_SUB [[IN0]]:_, [[IN6:%[0-9]+]]:_
# CHECK-WORKLIST-DAG: Changed: [[IN5]]:_(s8) = G_SUB [[OUT2:%[0-9]+]]:_, [[IN6]]:_
# CHECK-WORKLIST-DAG: Erasing: [[IN2]]:_(s32) = G_SEXT [[IN0]]:_(s8)
-# CHECK-WORKLIST-DAG: Changed: [[IN2]]:_(s32) = G_SEXTLOAD [[IN1]]:_(p0) :: (load 1 from %ir.addr)
+# CHECK-WORKLIST-DAG: Changed: [[IN2]]:_(s32) = G_SEXTLOAD [[IN1]]:_(p0){{.*}} :: (load 1 from %ir.addr)
# CHECK-WORKLIST-DAG: Created: [[OUT1]]:_(s8) = G_TRUNC [[IN2]]:_(s32)
# CHECK-WORKLIST-DAG: Created: [[OUT2]]:_(s8) = G_TRUNC [[IN2]]:_(s32)
# CHECK-WORKLIST: Try combining
diff --git a/llvm/test/CodeGen/AArch64/O0-pipeline.ll b/llvm/test/CodeGen/AArch64/O0-pipeline.ll
index 6d6ccea1e2ab..3398b516125d 100644
--- a/llvm/test/CodeGen/AArch64/O0-pipeline.ll
+++ b/llvm/test/CodeGen/AArch64/O0-pipeline.ll
@@ -1,4 +1,5 @@
-; RUN: llc -mtriple=arm64-- -O0 -debug-pass=Structure < %s -o /dev/null 2>&1 | grep -v "Verify generated machine code" | FileCheck %s
+; RUN: llc --debugify-and-strip-all-safe=0 -mtriple=arm64-- -O0 -debug-pass=Structure < %s -o /dev/null 2>&1 | \
+; RUN: grep -v "Verify generated machine code" | FileCheck %s
; REQUIRES: asserts
diff --git a/llvm/test/CodeGen/AArch64/O3-pipeline.ll b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
index 1ae3be1de9d1..6edcb7cac87e 100644
--- a/llvm/test/CodeGen/AArch64/O3-pipeline.ll
+++ b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
@@ -1,4 +1,5 @@
-; RUN: llc -mtriple=arm64-- -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | grep -v "Verify generated machine code" | FileCheck %s
+; RUN: llc --debugify-and-strip-all-safe=0 -mtriple=arm64-- -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | \
+; RUN: grep -v "Verify generated machine code" | FileCheck %s
; REQUIRES: asserts
diff --git a/llvm/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll b/llvm/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll
index 79cf99008433..e12fb7478d64 100644
--- a/llvm/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll
@@ -1,10 +1,12 @@
; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -pass-remarks-analysis=asm-printer \
+; RUN: --debugify-and-strip-all-safe=0 \
; RUN: -verify-machineinstrs \
; RUN: -pass-remarks-with-hotness=1 -asm-verbose=0 \
; RUN: -debug-only=lazy-machine-block-freq,block-freq \
; RUN: -debug-pass=Executions 2>&1 | FileCheck %s -check-prefix=HOTNESS
; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -pass-remarks-analysis=asm-printer \
+; RUN: --debugify-and-strip-all-safe=0 \
; RUN: -verify-machineinstrs \
; RUN: -pass-remarks-with-hotness=0 -asm-verbose=0 \
; RUN: -debug-only=lazy-machine-block-freq,block-freq \
diff --git a/llvm/test/CodeGen/AArch64/fastisel-debugvalue-undef.ll b/llvm/test/CodeGen/AArch64/fastisel-debugvalue-undef.ll
index 86aa7d15edbb..aceb85f4dd7f 100644
--- a/llvm/test/CodeGen/AArch64/fastisel-debugvalue-undef.ll
+++ b/llvm/test/CodeGen/AArch64/fastisel-debugvalue-undef.ll
@@ -12,14 +12,11 @@ define void @foo() !dbg !6 {
declare void @llvm.dbg.value(metadata, metadata, metadata)
!llvm.dbg.cu = !{!0}
-!llvm.debugify = !{!3, !4}
!llvm.module.flags = !{!5}
!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
!1 = !DIFile(filename: "t.ll", directory: "/")
!2 = !{}
-!3 = !{i32 2}
-!4 = !{i32 1}
!5 = !{i32 2, !"Debug Info Version", i32 3}
!6 = distinct !DISubprogram(name: "foo", linkageName: "foo", scope: null, file: !1, line: 1, type: !7, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8)
!7 = !DISubroutineType(types: !2)
diff --git a/llvm/test/CodeGen/AArch64/patchable-function-entry-empty.mir b/llvm/test/CodeGen/AArch64/patchable-function-entry-empty.mir
index 36513297edec..2db89d210316 100644
--- a/llvm/test/CodeGen/AArch64/patchable-function-entry-empty.mir
+++ b/llvm/test/CodeGen/AArch64/patchable-function-entry-empty.mir
@@ -5,12 +5,12 @@
# CHECK: name: empty
# CHECK: bb.0.entry
# CHECK: PATCHABLE_FUNCTION_ENTER{{$}}
-# CHECK-NEXT: RET undef $lr, debug-location !DILocation(line: 1,
+# CHECK-NEXT: RET undef $lr, debug-location !9
--- |
- define void @empty() #0 !dbg !7 {
+ define void @empty() #0 !dbg !6 {
entry:
- ret void, !dbg !10
+ ret void, !dbg !9
}
attributes #0 = { "patchable-function-entry"="1" }
@@ -20,11 +20,12 @@
!3 = !{i32 7, !"Dwarf Version", i32 4}
!4 = !{i32 2, !"Debug Info Version", i32 3}
!5 = !{i32 1, !"wchar_size", i32 4}
- !6 = !{!"clang version 11.0.0 "}
- !7 = distinct !DISubprogram(name: "empty", scope: !1, file: !1, line: 1, type: !8, scopeLine: 1, flags: DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2)
- !8 = !DISubroutineType(types: !9)
- !9 = !{null}
- !10 = !DILocation(line: 1, column: 61, scope: !7)
+ !6 = distinct !DISubprogram(name: "empty", scope: !1, file: !1, line: 1, type: !7, scopeLine: 1, flags: DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2)
+ !7 = !DISubroutineType(types: !8)
+ !8 = !{null}
+ !9 = !DILocation(line: 1, column: 61, scope: !6)
+ !llvm.dbg.cu = !{!0}
+ !llvm.module.flags = !{!3, !4, !5}
...
---
@@ -34,6 +35,6 @@ tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $lr
- RET undef $lr, debug-location !10
+ RET undef $lr, debug-location !9
...
diff --git a/llvm/test/CodeGen/AArch64/prologue-epilogue-remarks.mir b/llvm/test/CodeGen/AArch64/prologue-epilogue-remarks.mir
index ed139875d26a..4bc1b968d170 100644
--- a/llvm/test/CodeGen/AArch64/prologue-epilogue-remarks.mir
+++ b/llvm/test/CodeGen/AArch64/prologue-epilogue-remarks.mir
@@ -5,10 +5,10 @@
name: fun0
stack:
- { id: 0, type: default, offset: 0, size: 8, alignment: 4 }
-# CHECK: --- !Analysis
+# CHECK-LABEL: --- !Analysis
# CHECK-NEXT: Pass: prologepilog
# CHECK-NEXT: Name: StackSize
-# CHECK-NEXT: Function: fun0
+# CHECK: Function: fun0
# CHECK-NEXT: Args:
# CHECK-NEXT: - NumStackBytes: '16'
# CHECK-NEXT: - String: ' stack bytes in function'
@@ -23,10 +23,10 @@ body: |
name: fun1
stack:
- { id: 0, type: default, offset: 0, size: 19, alignment: 4 }
-# CHECK: --- !Analysis
+# CHECK-LABEL: --- !Analysis
# CHECK-NEXT: Pass: prologepilog
# CHECK-NEXT: Name: StackSize
-# CHECK-NEXT: Function: fun1
+# CHECK: Function: fun1
# CHECK-NEXT: Args:
# CHECK-NEXT: - NumStackBytes: '32'
# CHECK-NEXT: - String: ' stack bytes in function'
@@ -41,10 +41,10 @@ body: |
name: fun2
stack:
- { id: 0, type: default, offset: 0, size: 1024, alignment: 4 }
-# --- !Analysis
+# CHECK-LABEL: --- !Analysis
# CHECK: Pass: prologepilog
# CHECK-NEXT: Name: StackSize
-# CHECK-NEXT: Function: fun2
+# CHECK: Function: fun2
# CHECK-NEXT: Args:
# CHECK-NEXT: - NumStackBytes: '1040'
# CHECK-NEXT: - String: ' stack bytes in function'
diff --git a/llvm/test/CodeGen/AArch64/seqpairspill.mir b/llvm/test/CodeGen/AArch64/seqpairspill.mir
index 225e10ecfdb5..fdcb3dc61181 100644
--- a/llvm/test/CodeGen/AArch64/seqpairspill.mir
+++ b/llvm/test/CodeGen/AArch64/seqpairspill.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o - %s -mtriple=aarch64-- -mattr=+v8.1a -run-pass=greedy,virtregrewriter | FileCheck %s
+# RUN: llc --debugify-and-strip-all-safe=0 -o - %s -mtriple=aarch64-- -mattr=+v8.1a -run-pass=greedy,virtregrewriter | FileCheck %s
# Make sure spills/reloads from xseqpairs and wseqpairs work correctly.
---
# CHECK-LABEL: name: spill_reload_xseqpairs
diff --git a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-debug.mir b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-debug.mir
index 17a9c47a588a..e89c778c5366 100644
--- a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-debug.mir
+++ b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-debug.mir
@@ -11,6 +11,9 @@
!7 = !DILocalVariable(name: "x", arg: 1, scope: !5, file: !1, line: 1, type: !8)
!8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
!9 = !DILocation(line: 1, column: 1, scope: !5)
+ !10 = !{i32 2, !"Debug Info Version", i32 3}
+ !llvm.dbg.cu = !{!0}
+ !llvm.module.flags = !{!10}
---
# Check we do not crash when checking $noreg debug operands.
#
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