[llvm] ebf22a4 - [x86] add test for FP->int->FP casts; NFC (PR36617)

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2020-04-10T15:57:35-04:00
New Revision: ebf22a49357934b622f30ef715d56b92955fa661

URL: https://github.com/llvm/llvm-project/commit/ebf22a49357934b622f30ef715d56b92955fa661
DIFF: https://github.com/llvm/llvm-project/commit/ebf22a49357934b622f30ef715d56b92955fa661.diff

LOG: [x86] add test for FP->int->FP casts; NFC (PR36617)

Also, add a common prefix for SSE to reduce redundant CHECK lines.

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/ftrunc.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/ftrunc.ll b/llvm/test/CodeGen/X86/ftrunc.ll
index 0a1c1e2a851e..7c58f345cfe8 100644
--- a/llvm/test/CodeGen/X86/ftrunc.ll
+++ b/llvm/test/CodeGen/X86/ftrunc.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2    | FileCheck %s --check-prefix=SSE2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1  | FileCheck %s --check-prefix=SSE41
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx     | FileCheck %s --check-prefix=AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2    | FileCheck %s --check-prefixes=SSE,SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1  | FileCheck %s --check-prefixes=SSE,SSE41
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx     | FileCheck %s --check-prefixes=AVX1
 
 define float @trunc_unsigned_f32(float %x) #0 {
 ; SSE2-LABEL: trunc_unsigned_f32:
@@ -220,6 +220,24 @@ define <4 x double> @trunc_unsigned_v4f64(<4 x double> %x) #0 {
   ret <4 x double> %r
 }
 
+define float @trunc_signed_f32_no_fast_math(float %x) {
+; SSE-LABEL: trunc_signed_f32_no_fast_math:
+; SSE:       # %bb.0:
+; SSE-NEXT:    cvttss2si %xmm0, %eax
+; SSE-NEXT:    xorps %xmm0, %xmm0
+; SSE-NEXT:    cvtsi2ss %eax, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX1-LABEL: trunc_signed_f32_no_fast_math:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vcvttss2si %xmm0, %eax
+; AVX1-NEXT:    vcvtsi2ss %eax, %xmm1, %xmm0
+; AVX1-NEXT:    retq
+  %i = fptosi float %x to i32
+  %r = sitofp i32 %i to float
+  ret float %r
+}
+
 define float @trunc_signed_f32(float %x) #0 {
 ; SSE2-LABEL: trunc_signed_f32:
 ; SSE2:       # %bb.0:
@@ -350,21 +368,13 @@ define <4 x double> @trunc_signed_v4f64(<4 x double> %x) #0 {
 ; working based on its assumptions of float->int overflow.
 
 define float @trunc_unsigned_f32_disable_via_attr(float %x) #1 {
-; SSE2-LABEL: trunc_unsigned_f32_disable_via_attr:
-; SSE2:       # %bb.0:
-; SSE2-NEXT:    cvttss2si %xmm0, %rax
-; SSE2-NEXT:    movl %eax, %eax
-; SSE2-NEXT:    xorps %xmm0, %xmm0
-; SSE2-NEXT:    cvtsi2ss %rax, %xmm0
-; SSE2-NEXT:    retq
-;
-; SSE41-LABEL: trunc_unsigned_f32_disable_via_attr:
-; SSE41:       # %bb.0:
-; SSE41-NEXT:    cvttss2si %xmm0, %rax
-; SSE41-NEXT:    movl %eax, %eax
-; SSE41-NEXT:    xorps %xmm0, %xmm0
-; SSE41-NEXT:    cvtsi2ss %rax, %xmm0
-; SSE41-NEXT:    retq
+; SSE-LABEL: trunc_unsigned_f32_disable_via_attr:
+; SSE:       # %bb.0:
+; SSE-NEXT:    cvttss2si %xmm0, %rax
+; SSE-NEXT:    movl %eax, %eax
+; SSE-NEXT:    xorps %xmm0, %xmm0
+; SSE-NEXT:    cvtsi2ss %rax, %xmm0
+; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: trunc_unsigned_f32_disable_via_attr:
 ; AVX1:       # %bb.0:
@@ -378,19 +388,12 @@ define float @trunc_unsigned_f32_disable_via_attr(float %x) #1 {
 }
 
 define double @trunc_signed_f64_disable_via_attr(double %x) #1 {
-; SSE2-LABEL: trunc_signed_f64_disable_via_attr:
-; SSE2:       # %bb.0:
-; SSE2-NEXT:    cvttsd2si %xmm0, %rax
-; SSE2-NEXT:    xorps %xmm0, %xmm0
-; SSE2-NEXT:    cvtsi2sd %rax, %xmm0
-; SSE2-NEXT:    retq
-;
-; SSE41-LABEL: trunc_signed_f64_disable_via_attr:
-; SSE41:       # %bb.0:
-; SSE41-NEXT:    cvttsd2si %xmm0, %rax
-; SSE41-NEXT:    xorps %xmm0, %xmm0
-; SSE41-NEXT:    cvtsi2sd %rax, %xmm0
-; SSE41-NEXT:    retq
+; SSE-LABEL: trunc_signed_f64_disable_via_attr:
+; SSE:       # %bb.0:
+; SSE-NEXT:    cvttsd2si %xmm0, %rax
+; SSE-NEXT:    xorps %xmm0, %xmm0
+; SSE-NEXT:    cvtsi2sd %rax, %xmm0
+; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: trunc_signed_f64_disable_via_attr:
 ; AVX1:       # %bb.0:
@@ -404,4 +407,3 @@ define double @trunc_signed_f64_disable_via_attr(double %x) #1 {
 
 attributes #0 = { nounwind "no-signed-zeros-fp-math"="true" }
 attributes #1 = { nounwind "no-signed-zeros-fp-math"="true" "strict-float-cast-overflow"="false" }
-