[PATCH] D77888: Add -debugify-and-strip-all to add debug info before a pass and remove it after

[Daniel Sanders via Phabricator via llvm-commits]

dsanders created this revision.
dsanders added reviewers: aprantl, vsk, bogner.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, qcolombet.
Herald added a project: LLVM.

This allows us to test each backend pass under the presence
of debug info using pre-existing tests. The tests should not
fail as a result of this so long as it's true that debug info
does not affect CodeGen.

In practice, a few tests are sensitive to this:

- Tests that check the pass structure (e.g. O0-pipeline.ll)
- Tests that check --debug output. Specifically instruction dumps containing MMO's (e.g. prelegalizercombiner-extends.ll)
- Tests that contain debugify metadata as mir-strip-debug will remove it (e.g. fastisel-debugvalue-undef.ll)
- Tests with partial debug info (e.g. patchable-function-entry-empty.mir had debug info but no !llvm.dbg.cu)
- Tests that check optimization remarks overly strictly (e.g. prologue-epilogue-remarks.mir)
- Tests that would inject the pass in an unsafe region (e.g. seqpairspill.mir would inject between register alloc and virt reg rewriter)

In all cases, the checks can either be updated or
--debugify-and-strip-all-safe=0 can be used to avoid being
affected by something like llvm-lit -Dllc='llc --debugify-and-strip-all-safe'

I tested this without the lost debug locations verifier to
confirm that AArch64 behaviour is unaffected (with the fixes
in this patch) and with it to confirm it finds the problems
without the additional RUN lines we had before.

Depends on D77886 <https://reviews.llvm.org/D77886>, D77887 <https://reviews.llvm.org/D77887>, D77747 <https://reviews.llvm.org/D77747>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77888

Files:
  llvm/include/llvm/CodeGen/TargetPassConfig.h
  llvm/lib/CodeGen/MachineDebugify.cpp
  llvm/lib/CodeGen/MachineStripDebug.cpp
  llvm/lib/CodeGen/TargetPassConfig.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
  llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
  llvm/test/CodeGen/AArch64/O0-pipeline.ll
  llvm/test/CodeGen/AArch64/O3-pipeline.ll
  llvm/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll
  llvm/test/CodeGen/AArch64/fastisel-debugvalue-undef.ll
  llvm/test/CodeGen/AArch64/patchable-function-entry-empty.mir
  llvm/test/CodeGen/AArch64/prologue-epilogue-remarks.mir
  llvm/test/CodeGen/AArch64/seqpairspill.mir
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming-debug.mir

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