[PATCH] D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions.

[Paolo Savini via Phabricator via llvm-commits]

PaoloS marked 5 inline comments as done.
PaoloS added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rv64Zbs.ll:9
+
+define i64 @_sbset(i64 %a, i64 %b) nounwind {
+; RV64I-NOT:    sbset a0, a0, a1
----------------
lewis-revill wrote:
> I'm not certain what the underscore is for, assuming it's to avoid clashing with LLVM intrinsics? If so shouldn't all LLVM intrinsics which cause a clash have a lowering?
That was a very old design choice of mine to be sure to avoid conflicts, but I should have removed it after verifying that it doesn't clash at all. I'll remove the underscore and check again.


Repository:
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  https://reviews.llvm.org/D67348/new/

https://reviews.llvm.org/D67348