[PATCH] D76354: [WIP][RISCV][GlobalISel] Legalize types for ALU operations

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill marked an inline comment as done.
lewis-revill added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/GlobalISel/legalizer/alu32.mir:9
+  ; Extends only exhaustively tested for add to avoid excessive tests.
+  define void @add_i8() { entry: ret void }
+  define void @add_i8_signext() { entry: ret void }
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arsenm wrote:
> You don't need the IR section here
I didn't realise this, though I'm considering leaving it for consistency with tests in other backends? Also I am going to look into using the update_mir_test_checks tool instead.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D76354/new/

https://reviews.llvm.org/D76354