[llvm] 0aa0d70 - MIR: Use Register
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 8 19:07:41 PDT 2020
Author: Matt Arsenault
Date: 2020-04-08T22:07:26-04:00
New Revision: 0aa0d700678228261e08947914cc1dedd5db8ef5
URL: https://github.com/llvm/llvm-project/commit/0aa0d700678228261e08947914cc1dedd5db8ef5
DIFF: https://github.com/llvm/llvm-project/commit/0aa0d700678228261e08947914cc1dedd5db8ef5.diff
LOG: MIR: Use Register
Added:
Modified:
llvm/include/llvm/CodeGen/MIRParser/MIParser.h
llvm/lib/CodeGen/MIRParser/MIParser.cpp
llvm/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/MIRParser/MIParser.h b/llvm/include/llvm/CodeGen/MIRParser/MIParser.h
index 8ca665b23b28..590b3dcdd93b 100644
--- a/llvm/include/llvm/CodeGen/MIRParser/MIParser.h
+++ b/llvm/include/llvm/CodeGen/MIRParser/MIParser.h
@@ -16,6 +16,7 @@
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/Register.h"
#include "llvm/Support/Allocator.h"
namespace llvm {
@@ -40,8 +41,8 @@ struct VRegInfo {
const TargetRegisterClass *RC;
const RegisterBank *RegBank;
} D;
- unsigned VReg;
- unsigned PreferredReg = 0;
+ Register VReg;
+ Register PreferredReg;
};
using Name2RegClassMap = StringMap<const TargetRegisterClass *>;
@@ -55,7 +56,7 @@ struct PerTargetMIParsingState {
StringMap<unsigned> Names2InstrOpCodes;
/// Maps from register names to registers.
- StringMap<unsigned> Names2Regs;
+ StringMap<Register> Names2Regs;
/// Maps from register mask names to register masks.
StringMap<const uint32_t *> Names2RegMasks;
@@ -100,7 +101,7 @@ struct PerTargetMIParsingState {
/// Try to convert a register name to a register number. Return true if the
/// register name is invalid.
- bool getRegisterByName(StringRef RegName, unsigned &Reg);
+ bool getRegisterByName(StringRef RegName, Register &Reg);
/// Check if the given identifier is a name of a register mask.
///
@@ -164,7 +165,7 @@ struct PerFunctionMIParsingState {
PerTargetMIParsingState &Target;
DenseMap<unsigned, MachineBasicBlock *> MBBSlots;
- DenseMap<unsigned, VRegInfo *> VRegInfos;
+ DenseMap<Register, VRegInfo *> VRegInfos;
StringMap<VRegInfo *> VRegInfosNamed;
DenseMap<unsigned, int> FixedStackObjectSlots;
DenseMap<unsigned, int> StackObjectSlots;
@@ -178,7 +179,7 @@ struct PerFunctionMIParsingState {
const SlotMapping &IRSlots,
PerTargetMIParsingState &Target);
- VRegInfo &getVRegInfo(unsigned Num);
+ VRegInfo &getVRegInfo(Register Num);
VRegInfo &getVRegInfoNamed(StringRef RegName);
const Value *getIRValue(unsigned Slot);
};
@@ -216,10 +217,10 @@ bool parseMBBReference(PerFunctionMIParsingState &PFS,
SMDiagnostic &Error);
bool parseRegisterReference(PerFunctionMIParsingState &PFS,
- unsigned &Reg, StringRef Src,
+ Register &Reg, StringRef Src,
SMDiagnostic &Error);
-bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, unsigned &Reg,
+bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg,
StringRef Src, SMDiagnostic &Error);
bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS,
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index c948fbaac603..68de9f49fe48 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -122,7 +122,7 @@ void PerTargetMIParsingState::initNames2Regs() {
}
bool PerTargetMIParsingState::getRegisterByName(StringRef RegName,
- unsigned &Reg) {
+ Register &Reg) {
initNames2Regs();
auto RegInfo = Names2Regs.find(RegName);
if (RegInfo == Names2Regs.end())
@@ -321,7 +321,7 @@ PerFunctionMIParsingState::PerFunctionMIParsingState(MachineFunction &MF,
: MF(MF), SM(&SM), IRSlots(IRSlots), Target(T) {
}
-VRegInfo &PerFunctionMIParsingState::getVRegInfo(unsigned Num) {
+VRegInfo &PerFunctionMIParsingState::getVRegInfo(Register Num) {
auto I = VRegInfos.insert(std::make_pair(Num, nullptr));
if (I.second) {
MachineRegisterInfo &MRI = MF.getRegInfo();
@@ -426,9 +426,9 @@ class MIParser {
bool parseBasicBlocks();
bool parse(MachineInstr *&MI);
bool parseStandaloneMBB(MachineBasicBlock *&MBB);
- bool parseStandaloneNamedRegister(unsigned &Reg);
+ bool parseStandaloneNamedRegister(Register &Reg);
bool parseStandaloneVirtualRegister(VRegInfo *&Info);
- bool parseStandaloneRegister(unsigned &Reg);
+ bool parseStandaloneRegister(Register &Reg);
bool parseStandaloneStackObject(int &FI);
bool parseStandaloneMDNode(MDNode *&Node);
@@ -439,10 +439,10 @@ class MIParser {
bool parseBasicBlockLiveins(MachineBasicBlock &MBB);
bool parseBasicBlockSuccessors(MachineBasicBlock &MBB);
- bool parseNamedRegister(unsigned &Reg);
+ bool parseNamedRegister(Register &Reg);
bool parseVirtualRegister(VRegInfo *&Info);
bool parseNamedVirtualRegister(VRegInfo *&Info);
- bool parseRegister(unsigned &Reg, VRegInfo *&VRegInfo);
+ bool parseRegister(Register &Reg, VRegInfo *&VRegInfo);
bool parseRegisterFlag(unsigned &Flags);
bool parseRegisterClassOrBank(VRegInfo &RegInfo);
bool parseSubRegisterIndex(unsigned &SubReg);
@@ -474,7 +474,7 @@ class MIParser {
bool parseDILocation(MDNode *&Expr);
bool parseMetadataOperand(MachineOperand &Dest);
bool parseCFIOffset(int &Offset);
- bool parseCFIRegister(unsigned &Reg);
+ bool parseCFIRegister(Register &Reg);
bool parseCFIEscapeValues(std::string& Values);
bool parseCFIOperand(MachineOperand &Dest);
bool parseIRBlock(BasicBlock *&BB, const Function &F);
@@ -775,7 +775,7 @@ bool MIParser::parseBasicBlockLiveins(MachineBasicBlock &MBB) {
do {
if (Token.isNot(MIToken::NamedRegister))
return error("expected a named register");
- unsigned Reg = 0;
+ Register Reg;
if (parseNamedRegister(Reg))
return true;
lex();
@@ -1083,7 +1083,7 @@ bool MIParser::parseStandaloneMBB(MachineBasicBlock *&MBB) {
return false;
}
-bool MIParser::parseStandaloneNamedRegister(unsigned &Reg) {
+bool MIParser::parseStandaloneNamedRegister(Register &Reg) {
lex();
if (Token.isNot(MIToken::NamedRegister))
return error("expected a named register");
@@ -1107,7 +1107,7 @@ bool MIParser::parseStandaloneVirtualRegister(VRegInfo *&Info) {
return false;
}
-bool MIParser::parseStandaloneRegister(unsigned &Reg) {
+bool MIParser::parseStandaloneRegister(Register &Reg) {
lex();
if (Token.isNot(MIToken::NamedRegister) &&
Token.isNot(MIToken::VirtualRegister))
@@ -1158,7 +1158,7 @@ static const char *printImplicitRegisterFlag(const MachineOperand &MO) {
}
static std::string getRegisterName(const TargetRegisterInfo *TRI,
- unsigned Reg) {
+ Register Reg) {
assert(Register::isPhysicalRegister(Reg) && "expected phys reg");
return StringRef(TRI->getName(Reg)).lower();
}
@@ -1258,7 +1258,7 @@ bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) {
return false;
}
-bool MIParser::parseNamedRegister(unsigned &Reg) {
+bool MIParser::parseNamedRegister(Register &Reg) {
assert(Token.is(MIToken::NamedRegister) && "Needs NamedRegister token");
StringRef Name = Token.stringValue();
if (PFS.Target.getRegisterByName(Name, Reg))
@@ -1286,7 +1286,7 @@ bool MIParser::parseVirtualRegister(VRegInfo *&Info) {
return false;
}
-bool MIParser::parseRegister(unsigned &Reg, VRegInfo *&Info) {
+bool MIParser::parseRegister(Register &Reg, VRegInfo *&Info) {
switch (Token.kind()) {
case MIToken::underscore:
Reg = 0;
@@ -1480,7 +1480,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
}
if (!Token.isRegister())
return error("expected a register after register flags");
- unsigned Reg;
+ Register Reg;
VRegInfo *RegInfo;
if (parseRegister(Reg, RegInfo))
return true;
@@ -2173,10 +2173,10 @@ bool MIParser::parseCFIOffset(int &Offset) {
return false;
}
-bool MIParser::parseCFIRegister(unsigned &Reg) {
+bool MIParser::parseCFIRegister(Register &Reg) {
if (Token.isNot(MIToken::NamedRegister))
return error("expected a cfi register");
- unsigned LLVMReg;
+ Register LLVMReg;
if (parseNamedRegister(LLVMReg))
return true;
const auto *TRI = MF.getSubtarget().getRegisterInfo();
@@ -2208,7 +2208,7 @@ bool MIParser::parseCFIOperand(MachineOperand &Dest) {
auto Kind = Token.kind();
lex();
int Offset;
- unsigned Reg;
+ Register Reg;
unsigned CFIIndex;
switch (Kind) {
case MIToken::kw_cfi_same_value:
@@ -2274,7 +2274,7 @@ bool MIParser::parseCFIOperand(MachineOperand &Dest) {
CFIIndex = MF.addFrameInst(MCCFIInstruction::createUndefined(nullptr, Reg));
break;
case MIToken::kw_cfi_register: {
- unsigned Reg2;
+ Register Reg2;
if (parseCFIRegister(Reg) || expectAndConsume(MIToken::comma) ||
parseCFIRegister(Reg2))
return true;
@@ -2504,7 +2504,7 @@ bool MIParser::parseCustomRegisterMaskOperand(MachineOperand &Dest) {
while (true) {
if (Token.isNot(MIToken::NamedRegister))
return error("expected a named register");
- unsigned Reg;
+ Register Reg;
if (parseNamedRegister(Reg))
return true;
lex();
@@ -2530,7 +2530,7 @@ bool MIParser::parseLiveoutRegisterMaskOperand(MachineOperand &Dest) {
while (true) {
if (Token.isNot(MIToken::NamedRegister))
return error("expected a named register");
- unsigned Reg;
+ Register Reg;
if (parseNamedRegister(Reg))
return true;
lex();
@@ -3207,13 +3207,13 @@ bool llvm::parseMBBReference(PerFunctionMIParsingState &PFS,
}
bool llvm::parseRegisterReference(PerFunctionMIParsingState &PFS,
- unsigned &Reg, StringRef Src,
+ Register &Reg, StringRef Src,
SMDiagnostic &Error) {
return MIParser(PFS, Error, Src).parseStandaloneRegister(Reg);
}
bool llvm::parseNamedRegisterReference(PerFunctionMIParsingState &PFS,
- unsigned &Reg, StringRef Src,
+ Register &Reg, StringRef Src,
SMDiagnostic &Error) {
return MIParser(PFS, Error, Src).parseStandaloneNamedRegister(Reg);
}
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 135b2f2234af..5b6f71a2a013 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -375,7 +375,7 @@ bool MIRParserImpl::initializeCallSiteInfo(
" is not a call instruction");
MachineFunction::CallSiteInfo CSInfo;
for (auto ArgRegPair : YamlCSInfo.ArgForwardingRegs) {
- unsigned Reg = 0;
+ Register Reg;
if (parseNamedRegisterReference(PFS, Reg, ArgRegPair.Reg.Value, Error))
return error(Error, ArgRegPair.Reg.SourceRange);
CSInfo.emplace_back(Reg, ArgRegPair.ArgNo);
@@ -557,10 +557,10 @@ bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
// Parse the liveins.
for (const auto &LiveIn : YamlMF.LiveIns) {
- unsigned Reg = 0;
+ Register Reg;
if (parseNamedRegisterReference(PFS, Reg, LiveIn.Register.Value, Error))
return error(Error, LiveIn.Register.SourceRange);
- unsigned VReg = 0;
+ Register VReg;
if (!LiveIn.VirtualRegister.Value.empty()) {
VRegInfo *Info;
if (parseVirtualRegisterReference(PFS, Info, LiveIn.VirtualRegister.Value,
@@ -576,7 +576,7 @@ bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
if (YamlMF.CalleeSavedRegisters) {
SmallVector<MCPhysReg, 16> CalleeSavedRegisters;
for (const auto &RegSource : YamlMF.CalleeSavedRegisters.getValue()) {
- unsigned Reg = 0;
+ Register Reg;
if (parseNamedRegisterReference(PFS, Reg, RegSource.Value, Error))
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
@@ -594,7 +594,7 @@ bool MIRParserImpl::setupRegisterInfo(const PerFunctionMIParsingState &PFS,
bool Error = false;
// Create VRegs
auto populateVRegInfo = [&] (const VRegInfo &Info, Twine Name) {
- unsigned Reg = Info.VReg;
+ Register Reg = Info.VReg;
switch (Info.Kind) {
case VRegInfo::UNKNOWN:
error(Twine("Cannot determine class/bank of virtual register ") +
@@ -765,7 +765,7 @@ bool MIRParserImpl::parseCalleeSavedRegister(PerFunctionMIParsingState &PFS,
const yaml::StringValue &RegisterSource, bool IsRestored, int FrameIdx) {
if (RegisterSource.Value.empty())
return false;
- unsigned Reg = 0;
+ Register Reg;
SMDiagnostic Error;
if (parseNamedRegisterReference(PFS, Reg, RegisterSource.Value, Error))
return error(Error, RegisterSource.SourceRange);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index f85c088fd53f..89c45de504df 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1069,7 +1069,7 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
// FIXME: Update parseNamedRegsiterReference to take a Register.
- unsigned TempReg;
+ Register TempReg;
if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
SourceRange = RegName.SourceRange;
return true;
@@ -1120,7 +1120,7 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
return false;
if (A->IsRegister) {
- unsigned Reg;
+ Register Reg;
if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
SourceRange = A->RegisterName.SourceRange;
return true;
More information about the llvm-commits
mailing list