[PATCH] D76822: [VE] Update lea/load/store instructions

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 marked an inline comment as done.
kaz7 added inline comments.


================
Comment at: llvm/lib/Target/VE/VEISelDAGToDAG.cpp:159
+
   if (Addr.getOpcode() == ISD::ADD) {
     if (Addr.getOperand(0).getOpcode() == VEISD::Lo ||
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kaz7 wrote:
> simoll wrote:
> > kaz7 wrote:
> > > simoll wrote:
> > > > This is a generalized version of `SelectionDAG::isBaseWithConstantOffset`. I suppose this code (up until line 177) should be moved into SelectionDAG, eg as `SelectionDAG::isBaseWithOffset`.
> > > > You can do that in a followup patch.
> > > Regarding to isBaseWithOffset, I'll try that.  Should I submit them as independent patch or just append modifications on SelectionDAG in this patch?
> > Better make it a separate patch for Phabricator after this patch is committed.
> I will do.  Thanks.
Today I checked other architecture implementations to consider how add isBaseWithOffset function.  However, it looks like only ARM, VE, and X86 support register + register instructions, and all other architecture has difficulties to use isBaseWithOffst function even if I add it.  How do you think?  Should I add the function?


Repository:
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  https://reviews.llvm.org/D76822/new/

https://reviews.llvm.org/D76822