[PATCH] D77300: [X86] Improve combineVectorShiftImm

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:40883
+      (!LogicalShift && ISD::isBuildVectorAllOnes(N0.getNode())))
     return N0;
 
----------------
foad wrote:
> RKSimon wrote:
> > ISD::isBuildVectorAll* leaves UNDEFs in there - we must generate the constant
> I don't quite understand why. If there are undefs in there then we will effectively be folding (VSRAI undef, C) -> undef (for some lanes). Isn't that allowed?
More clearly we're guaranteeing that for logical shifts that the upper bits will be zero. I'd recommend playing it safe as we've been hit by these things before (PR43159/PR43177) as SimplifyDemandedBits becomes more capable:
```
// Shift N0 by zero -> N0.
if (!ShiftVal)
  return N0;
// Shift zero -> zero.
if (ISD::isBuildVectorAllZeros(N0.getNode()))
  return DAG.getConstant(0, SDLoc(N), VT);
// (VSRAI -1, C) -> -1
if (!LogicalShift && ISD::isBuildVectorAllOnes(N0.getNode()))
  return DAG.getConstant(-1, SDLoc(N), VT);
```



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  https://reviews.llvm.org/D77300/new/

https://reviews.llvm.org/D77300