[PATCH] D77301: [TargetLowering] Improve expansion of FSHL/FSHR

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
foad added reviewers: RKSimon, craig.topper, arsenm, spatel.
Herald added subscribers: llvm-commits, hiraditya, wdng.
Herald added a project: LLVM.
foad added a parent revision: D77300: [X86] Improve combineVectorShiftImm.
foad marked an inline comment as done.
foad added inline comments.


================
Comment at: llvm/test/CodeGen/X86/fshl.ll:123-124
+; X86-SLOW-NEXT:    shrl %eax
+; X86-SLOW-NEXT:    andb $31, %cl
+; X86-SLOW-NEXT:    xorb $31, %cl
+; X86-SLOW-NEXT:    shrl %cl, %eax
----------------
The `andb` is redundant here and in a bunch of other i32/i64 test cases. I would have thought the simplifyDemandedBits machinery could work that out. Any ideas why this isn't already working?


Use an extra shift-by-1 instead of a compare and select to handle the
shift-by-zero case. This sometimes saves one instruction (if the compare
couldn't be combined with a previous instruction). It also works better
on targets that don't have good select instructions.

Note that currently this change doesn't affect most targets because
expandFunnelShift is not used because funnel shift intrinsics are
lowered early in SelectionDAGBuilder. But there is work afoot to change
that; see D77152 <https://reviews.llvm.org/D77152>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77301

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/X86/fshl.ll
  llvm/test/CodeGen/X86/fshr.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D77301.254496.patch
Type: text/x-patch
Size: 22361 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200402/18efe91e/attachment-0001.bin>