[PATCH] D71767: [POC][SVE] Allow code generation for fixed length vectorised loops [Patch 2/2].

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.



> What about a scheme where we make the fixed-width vector types proper subregs of the scalable types? That way we can add the fixed-width types to the calling conventions and register classes. Would that be of interest you?
> 
> It would be similar to X86's XMM->YMM->ZMM registers (i.e. 128b->256b->512b), except that all of SVE's sub-registers would print the same register name. it's a little hacky, but might polish

The problem here is what fixed-width vector types would you use?  The mapping would be dependent on the target.  We did experiment with HwMode but it didn't work out.  At this stage I think the simplest option is for the vectorised functions to use scalable argument and then provide a way to insert/extract fixed width vectors into/from them.  During code generation these insert/extract operations will become _SUBVECTOR operations that should generate no code. This is akin to the general philosophy I have used for fixed width code generation.


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https://reviews.llvm.org/D71767