[PATCH] D77092: [SelectionDAG] Add an assert that the input VT and output VT for ISD::FREEZE are the same.

Juneyoung Lee via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Mar 30 18:35:48 PDT 2020

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aqjune accepted this revision.
aqjune added a comment.
This revision is now accepted and ready to land.

LGTM


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  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D77092/new/

https://reviews.llvm.org/D77092

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