[llvm] cce3d96 - GlobalISel: Add matcher for G_SHL

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-03-29T14:03:07-04:00
New Revision: cce3d96bcc6585e5f134fc093ec50813659c5c5e

URL: https://github.com/llvm/llvm-project/commit/cce3d96bcc6585e5f134fc093ec50813659c5c5e
DIFF: https://github.com/llvm/llvm-project/commit/cce3d96bcc6585e5f134fc093ec50813659c5c5e.diff

LOG: GlobalISel: Add matcher for G_SHL

Added: 
    

Modified: 
    llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
    llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp

Removed: 
    


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diff  --git a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
index 65b1948a1967..1fae635f48fd 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
@@ -241,6 +241,12 @@ inline BinaryOp_match<LHS, RHS, TargetOpcode::G_OR, true> m_GOr(const LHS &L,
   return BinaryOp_match<LHS, RHS, TargetOpcode::G_OR, true>(L, R);
 }
 
+template <typename LHS, typename RHS>
+inline BinaryOp_match<LHS, RHS, TargetOpcode::G_SHL, false>
+m_GShl(const LHS &L, const RHS &R) {
+  return BinaryOp_match<LHS, RHS, TargetOpcode::G_SHL, false>(L, R);
+}
+
 template <typename LHS, typename RHS>
 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_LSHR, false>
 m_GLShr(const LHS &L, const RHS &R) {

diff  --git a/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp b/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp
index 172eca46b4a9..6a54084cacaf 100644
--- a/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp
@@ -137,6 +137,14 @@ TEST_F(AArch64GISelMITest, MatchBinaryOp) {
   EXPECT_TRUE(match);
   EXPECT_EQ(Src0, Copies[0]);
   EXPECT_EQ(Src1, TruncCopy1.getReg(0));
+
+  // Match shl, and make sure a 
diff erent shift amount type works.
+  auto Shl = B.buildShl(s64, Copies[0], TruncCopy1);
+  match = mi_match(Shl.getReg(0), *MRI,
+                   m_GShl(m_Reg(Src0), m_Reg(Src1)));
+  EXPECT_TRUE(match);
+  EXPECT_EQ(Src0, Copies[0]);
+  EXPECT_EQ(Src1, TruncCopy1.getReg(0));
 }
 
 TEST_F(AArch64GISelMITest, MatchICmp) {