[llvm] 0b68ca5 - AMDGPU: Add some additional tests for v_cvt_ubyte* formation
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 29 11:03:19 PDT 2020
Author: Matt Arsenault
Date: 2020-03-29T14:03:07-04:00
New Revision: 0b68ca516239829e6a6d5a79100151eb70a53c9e
URL: https://github.com/llvm/llvm-project/commit/0b68ca516239829e6a6d5a79100151eb70a53c9e
DIFF: https://github.com/llvm/llvm-project/commit/0b68ca516239829e6a6d5a79100151eb70a53c9e.diff
LOG: AMDGPU: Add some additional tests for v_cvt_ubyte* formation
Use functions now that we have them for less boilerplate in the
output.
Added:
Modified:
llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
index 41a6b8c291a9..15d88b52db25 100644
--- a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
@@ -1,10 +1,386 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s -allow-deprecated-dag-overlap -check-prefixes=GCN,SI
-; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -allow-deprecated-dag-overlap -check-prefixes=GCN,VI
+; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,SI
+; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,VI
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone
+define float @v_uitofp_i32_to_f32_mask255(i32 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_i32_to_f32_mask255:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %masked = and i32 %arg0, 255
+ %cvt = uitofp i32 %masked to float
+ ret float %cvt
+}
+
+define float @v_sitofp_i32_to_f32_mask255(i32 %arg0) nounwind {
+; GCN-LABEL: v_sitofp_i32_to_f32_mask255:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %masked = and i32 %arg0, 255
+ %cvt = sitofp i32 %masked to float
+ ret float %cvt
+}
+
+define float @v_uitofp_to_f32_lshr7_mask255(i32 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_to_f32_lshr7_mask255:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 7, v0
+; GCN-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %lshr.7 = lshr i32 %arg0, 7
+ %masked = and i32 %lshr.7, 255
+ %cvt = uitofp i32 %masked to float
+ ret float %cvt
+}
+
+define float @v_uitofp_to_f32_lshr8_mask255(i32 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_to_f32_lshr8_mask255:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte1_e32 v0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %lshr.8 = lshr i32 %arg0, 8
+ %masked = and i32 %lshr.8, 255
+ %cvt = uitofp i32 %masked to float
+ ret float %cvt
+}
+
+define float @v_uitofp_to_f32_multi_use_lshr8_mask255(i32 %arg0) nounwind {
+; SI-LABEL: v_uitofp_to_f32_multi_use_lshr8_mask255:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; SI-NEXT: v_cvt_f32_ubyte1_e32 v0, v0
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_uitofp_to_f32_multi_use_lshr8_mask255:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; VI-NEXT: v_cvt_f32_ubyte1_e32 v0, v0
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_setpc_b64 s[30:31]
+ %lshr.8 = lshr i32 %arg0, 8
+ store i32 %lshr.8, i32 addrspace(1)* undef
+ %masked = and i32 %lshr.8, 255
+ %cvt = uitofp i32 %masked to float
+ ret float %cvt
+}
+
+define float @v_uitofp_to_f32_lshr16_mask255(i32 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_to_f32_lshr16_mask255:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte2_e32 v0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %lshr.16 = lshr i32 %arg0, 16
+ %masked = and i32 %lshr.16, 255
+ %cvt = uitofp i32 %masked to float
+ ret float %cvt
+}
+
+define float @v_uitofp_to_f32_lshr24_mask255(i32 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_to_f32_lshr24_mask255:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte3_e32 v0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %lshr.16 = lshr i32 %arg0, 24
+ %masked = and i32 %lshr.16, 255
+ %cvt = uitofp i32 %masked to float
+ ret float %cvt
+}
+
+define float @v_uitofp_i8_to_f32(i8 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_i8_to_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %cvt = uitofp i8 %arg0 to float
+ ret float %cvt
+}
+
+define <2 x float> @v_uitofp_v2i8_to_v2f32(i16 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_v2i8_to_v2f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte0_e32 v2, v0
+; GCN-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
+; GCN-NEXT: v_mov_b32_e32 v0, v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %val = bitcast i16 %arg0 to <2 x i8>
+ %cvt = uitofp <2 x i8> %val to <2 x float>
+ ret <2 x float> %cvt
+}
+
+define <3 x float> @v_uitofp_v3i8_to_v3f32(i32 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_v3i8_to_v3f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte0_e32 v3, v0
+; GCN-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
+; GCN-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
+; GCN-NEXT: v_mov_b32_e32 v0, v3
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %trunc = trunc i32 %arg0 to i24
+ %val = bitcast i24 %trunc to <3 x i8>
+ %cvt = uitofp <3 x i8> %val to <3 x float>
+ ret <3 x float> %cvt
+}
+
+define <4 x float> @v_uitofp_v4i8_to_v4f32(i32 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_v4i8_to_v4f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte0_e32 v4, v0
+; GCN-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
+; GCN-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
+; GCN-NEXT: v_cvt_f32_ubyte3_e32 v3, v0
+; GCN-NEXT: v_mov_b32_e32 v0, v4
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %val = bitcast i32 %arg0 to <4 x i8>
+ %cvt = uitofp <4 x i8> %val to <4 x float>
+ ret <4 x float> %cvt
+}
+
+define <4 x float> @v_uitofp_unpack_i32_to_v4f32(i32 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_unpack_i32_to_v4f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte0_e32 v4, v0
+; GCN-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
+; GCN-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
+; GCN-NEXT: v_cvt_f32_ubyte3_e32 v3, v0
+; GCN-NEXT: v_mov_b32_e32 v0, v4
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %mask.arg0 = and i32 %arg0, 255
+ %cvt0 = uitofp i32 %mask.arg0 to float
+
+ %lshr.8 = lshr i32 %arg0, 8
+ %mask.lshr.8 = and i32 %lshr.8, 255
+ %cvt1 = uitofp i32 %mask.lshr.8 to float
+
+ %lshr.16 = lshr i32 %arg0, 16
+ %mask.lshr.16 = and i32 %lshr.16, 255
+ %cvt2 = uitofp i32 %mask.lshr.16 to float
+
+ %lshr.24 = lshr i32 %arg0, 24
+ %mask.lshr.24 = and i32 %lshr.24, 255
+ %cvt3 = uitofp i32 %mask.lshr.24 to float
+
+ %ins.0 = insertelement <4 x float> undef, float %cvt0, i32 0
+ %ins.1 = insertelement <4 x float> %ins.0, float %cvt1, i32 1
+ %ins.2 = insertelement <4 x float> %ins.1, float %cvt2, i32 2
+ %ins.3 = insertelement <4 x float> %ins.2, float %cvt3, i32 3
+ ret <4 x float> %ins.3
+}
+
+define half @v_uitofp_i32_to_f16_mask255(i32 %arg0) nounwind {
+; SI-LABEL: v_uitofp_i32_to_f16_mask255:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_uitofp_i32_to_f16_mask255:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cvt_f32_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+; VI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
+ %masked = and i32 %arg0, 255
+ %cvt = uitofp i32 %masked to half
+ ret half %cvt
+}
+
+define half @v_sitofp_i32_to_f16_mask255(i32 %arg0) nounwind {
+; SI-LABEL: v_sitofp_i32_to_f16_mask255:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_sitofp_i32_to_f16_mask255:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cvt_f32_i32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+; VI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
+ %masked = and i32 %arg0, 255
+ %cvt = sitofp i32 %masked to half
+ ret half %cvt
+}
+
+define half @v_uitofp_to_f16_lshr8_mask255(i32 %arg0) nounwind {
+; SI-LABEL: v_uitofp_to_f16_lshr8_mask255:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_ubyte1_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_uitofp_to_f16_lshr8_mask255:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cvt_f32_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+; VI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
+ %lshr.8 = lshr i32 %arg0, 8
+ %masked = and i32 %lshr.8, 255
+ %cvt = uitofp i32 %masked to half
+ ret half %cvt
+}
+
+define half @v_uitofp_to_f16_lshr16_mask255(i32 %arg0) nounwind {
+; SI-LABEL: v_uitofp_to_f16_lshr16_mask255:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_ubyte2_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_uitofp_to_f16_lshr16_mask255:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cvt_f32_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+; VI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
+ %lshr.16 = lshr i32 %arg0, 16
+ %masked = and i32 %lshr.16, 255
+ %cvt = uitofp i32 %masked to half
+ ret half %cvt
+}
+
+define half @v_uitofp_to_f16_lshr24_mask255(i32 %arg0) nounwind {
+; SI-LABEL: v_uitofp_to_f16_lshr24_mask255:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_ubyte3_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_uitofp_to_f16_lshr24_mask255:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cvt_f32_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+; VI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
+ %lshr.16 = lshr i32 %arg0, 24
+ %masked = and i32 %lshr.16, 255
+ %cvt = uitofp i32 %masked to half
+ ret half %cvt
+}
+
+define half @v_uitofp_i8_to_f16(i8 %arg0) nounwind {
+; SI-LABEL: v_uitofp_i8_to_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_uitofp_i8_to_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cvt_f16_u16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+; VI-NEXT: s_setpc_b64 s[30:31]
+ %cvt = uitofp i8 %arg0 to half
+ ret half %cvt
+}
+
+define double @v_uitofp_i32_to_f64_mask255(i32 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_i32_to_f64_mask255:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %masked = and i32 %arg0, 255
+ %cvt = uitofp i32 %masked to double
+ ret double %cvt
+}
+
+define double @v_uitofp_to_f64_lshr8_mask255(i32 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_to_f64_lshr8_mask255:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_bfe_u32 v0, v0, 8, 8
+; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %lshr.8 = lshr i32 %arg0, 8
+ %masked = and i32 %lshr.8, 255
+ %cvt = uitofp i32 %masked to double
+ ret double %cvt
+}
+
+define double @v_uitofp_to_f64_lshr16_mask255(i32 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_to_f64_lshr16_mask255:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_bfe_u32 v0, v0, 16, 8
+; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %lshr.16 = lshr i32 %arg0, 16
+ %masked = and i32 %lshr.16, 255
+ %cvt = uitofp i32 %masked to double
+ ret double %cvt
+}
+
+define double @v_uitofp_to_f64_lshr24_mask255(i32 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_to_f64_lshr24_mask255:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 24, v0
+; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %lshr.16 = lshr i32 %arg0, 24
+ %masked = and i32 %lshr.16, 255
+ %cvt = uitofp i32 %masked to double
+ ret double %cvt
+}
+
+define double @v_uitofp_i8_to_f64(i8 %arg0) nounwind {
+; SI-LABEL: v_uitofp_i8_to_f64:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_uitofp_i8_to_f64:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, 0xffff
+; VI-NEXT: v_and_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
+; VI-NEXT: s_setpc_b64 s[30:31]
+ %cvt = uitofp i8 %arg0 to double
+ ret double %cvt
+}
+
define amdgpu_kernel void @load_i8_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {
; SI-LABEL: load_i8_to_f32:
; SI: ; %bb.0:
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