[PATCH] D76910: [ARM] Make remaining MVE instruction predictable

[Dave Green via Phabricator via llvm-commits]

dmgreen marked an inline comment as done.
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In D76910#1945744 <https://reviews.llvm.org/D76910#1945744>, @samparker wrote:

> Are we talking about CONSTRAINED_UNPREDICTABLE here? If so, why is this modeled with hasSideEffects?


No, different thing. It is if the instruction might do things we don't model directly. Read memory, operate on unmodelled flags, those kind of things. They essentially create scheduling barriers, which is why it's good to remove them.

In D76910#1945681 <https://reviews.llvm.org/D76910#1945681>, @simon_tatham wrote:

> Do you understand //why// all those test outputs have changed as a side effect of this?


The VMOV lane change I believe. They come from COPY's, not from being directly lowered. Essentially different scheduling graph -> different ordering. I don't think the tests in question are particularly interesting, just showing expansion of VLDn's that we don't have direct support for. With the schedules we have downstream this seems to help in a few cases (so long as D76909 <https://reviews.llvm.org/D76909> is fixed).



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Comment at: llvm/unittests/Target/ARM/MachineInstrTest.cpp:867
+      continue;
+    if (UnpredicatableOpcodes.count(Op))
+      continue;
----------------
simon_tatham wrote:
> Another instance of the same typo.
Ah thanks. I've been doing that a lot lately.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76910/new/

https://reviews.llvm.org/D76910