[PATCH] D76767: [RISCV] Support negative constants in CompressInstEmitter

[Simon Cook via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG1e303962232d: [RISCV] Support negative constants in CompressInstEmitter (authored by simoncook).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76767/new/

https://reviews.llvm.org/D76767

Files:
  llvm/utils/TableGen/RISCVCompressInstEmitter.cpp


Index: llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
===================================================================
--- llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
+++ llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
@@ -85,7 +85,7 @@
     MapKind Kind;
     union {
       unsigned Operand; // Operand number mapped to.
-      uint64_t Imm;     // Integer immediate value.
+      int64_t Imm;      // Integer immediate value.
       Record *Reg;      // Physical register.
     } Data;
     int TiedOpIdx = -1; // Tied operand index within the instruction.


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