[PATCH] D76068: [ARM][MachineOutliner] Add NoLRSave and Register modes.

[Yvan Roux via Phabricator via llvm-commits]

yroux marked 2 inline comments as done.
yroux added a comment.

Thanks for the review Jessica and Sam,

I'll split it into two separate patches and thanks for the pointer to llvm/utils/update_mir_test_checks.py !



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Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:5689
+    unsigned NumBytesNoStackCalls = 0;
+    std::vector<outliner::Candidate> CandidatesWithoutStackFixups;
+
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samparker wrote:
> SmallVector instead?
well, this is passed as a parameter to outliner::OutlinedFunction which takes an std::Vector, maybe a SmallVector can used there instead but I think it should be done in another patch


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Comment at: llvm/test/CodeGen/ARM/machine-outliner-nosave-and-regs.mir:3
+# RUN: %s -o - | FileCheck %s
+# RUN: llc -mtriple=thumbv7-- -run-pass=machine-outliner -verify-machineinstrs \
+# RUN: %s -o - | FileCheck %s
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samparker wrote:
> I think it would be good practise to add a thumb-1 target to any of the tests added.
Agreed


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https://reviews.llvm.org/D76068