[llvm] 4a6ebc0 - [MachinePipeliner] Fix a bug in Output Dependency chains

[Jinsong Ji via llvm-commits]

Author: Lama
Date: 2020-03-24T14:37:50Z
New Revision: 4a6ebc03ba89340e119b3c2c6b8a6c721fff5fd5

URL: https://github.com/llvm/llvm-project/commit/4a6ebc03ba89340e119b3c2c6b8a6c721fff5fd5
DIFF: https://github.com/llvm/llvm-project/commit/4a6ebc03ba89340e119b3c2c6b8a6c721fff5fd5.diff

LOG: [MachinePipeliner] Fix a bug in Output Dependency chains

The current implementation collects all Preds/Succs of a Dep of kind Output, creating a long chain and subsequently a schedule with an unnecessarily large II.
Was this done on purpose for a reason I'm missing?

Reviewed By: bcahoon

Differential Revision: https://reviews.llvm.org/D75424

Added: 
    

Modified: 
    llvm/lib/CodeGen/MachinePipeliner.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index 4efa99a9887d..41a53d1edde6 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -2368,7 +2368,7 @@ int SMSchedule::earliestCycleInChain(const SDep &Dep) {
       continue;
     EarlyCycle = std::min(EarlyCycle, it->second);
     for (const auto &PI : PrevSU->Preds)
-      if (PI.getKind() == SDep::Order || Dep.getKind() == SDep::Output)
+      if (PI.getKind() == SDep::Order || PI.getKind() == SDep::Output)
         Worklist.push_back(PI);
     Visited.insert(PrevSU);
   }
@@ -2391,7 +2391,7 @@ int SMSchedule::latestCycleInChain(const SDep &Dep) {
       continue;
     LateCycle = std::max(LateCycle, it->second);
     for (const auto &SI : SuccSU->Succs)
-      if (SI.getKind() == SDep::Order || Dep.getKind() == SDep::Output)
+      if (SI.getKind() == SDep::Order || SI.getKind() == SDep::Output)
         Worklist.push_back(SI);
     Visited.insert(SuccSU);
   }