[PATCH] D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension

[Paolo Savini via Phabricator via llvm-commits]

PaoloS updated this revision to Diff 252200.
PaoloS marked an inline comment as done and an inline comment as not done.
PaoloS added a comment.

- Sorted the definitions of the instructions and the MC tests according to the order of the encodings in the manual.
- Improved the names of the instruction templates.
- Removed unused operand types and instruction templates.
- The features hasSideEffects, mayLoad and mayStore are now set only on the templates that need it.
- Renamed all the immediate parameters in the templates as 'shamt', for uniformity.
- Split the funct12 field of the unary instruction template into two fields of 7 and 5 bits. For conformity to the manual and for maintainability.
- Added a 4-bit immediate operand for the 32 bit shuffle.
- Added constraints on the size of the immediate operands.
- Added tests on the constraints of the immediate operands.
- Renamed most registers in the tests for uniformity.
- Removed the compressed instructions as they are still a proposal for the C extension and still cause encoding conflicts with the ones aready implemented there.
- Removed tests of compressed instructions.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65649/new/

https://reviews.llvm.org/D65649

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/rv32Zbb-invalid.s
  llvm/test/MC/RISCV/rv32Zbb-valid.s
  llvm/test/MC/RISCV/rv32Zbbp-invalid.s
  llvm/test/MC/RISCV/rv32Zbbp-valid.s
  llvm/test/MC/RISCV/rv32Zbc-invalid.s
  llvm/test/MC/RISCV/rv32Zbc-valid.s
  llvm/test/MC/RISCV/rv32Zbe-invalid.s
  llvm/test/MC/RISCV/rv32Zbe-valid.s
  llvm/test/MC/RISCV/rv32Zbf-invalid.s
  llvm/test/MC/RISCV/rv32Zbf-valid.s
  llvm/test/MC/RISCV/rv32Zbp-invalid.s
  llvm/test/MC/RISCV/rv32Zbp-valid.s
  llvm/test/MC/RISCV/rv32Zbr-invalid.s
  llvm/test/MC/RISCV/rv32Zbr-valid.s
  llvm/test/MC/RISCV/rv32Zbs-invalid.s
  llvm/test/MC/RISCV/rv32Zbs-valid.s
  llvm/test/MC/RISCV/rv32Zbt-invalid.s
  llvm/test/MC/RISCV/rv32Zbt-valid.s
  llvm/test/MC/RISCV/rv32b-aliases-valid.s
  llvm/test/MC/RISCV/rv64Zbb-invalid.s
  llvm/test/MC/RISCV/rv64Zbb-valid.s
  llvm/test/MC/RISCV/rv64Zbbp-invalid.s
  llvm/test/MC/RISCV/rv64Zbbp-valid.s
  llvm/test/MC/RISCV/rv64Zbc-invalid.s
  llvm/test/MC/RISCV/rv64Zbc-valid.s
  llvm/test/MC/RISCV/rv64Zbe-invalid.s
  llvm/test/MC/RISCV/rv64Zbe-valid.s
  llvm/test/MC/RISCV/rv64Zbf-invalid.s
  llvm/test/MC/RISCV/rv64Zbf-valid.s
  llvm/test/MC/RISCV/rv64Zbm-invalid.s
  llvm/test/MC/RISCV/rv64Zbm-valid.s
  llvm/test/MC/RISCV/rv64Zbp-invalid.s
  llvm/test/MC/RISCV/rv64Zbp-valid.s
  llvm/test/MC/RISCV/rv64Zbr-invalid.s
  llvm/test/MC/RISCV/rv64Zbr-valid.s
  llvm/test/MC/RISCV/rv64Zbs-invalid.s
  llvm/test/MC/RISCV/rv64Zbs-valid.s
  llvm/test/MC/RISCV/rv64Zbt-invalid.s
  llvm/test/MC/RISCV/rv64Zbt-valid.s
  llvm/test/MC/RISCV/rv64b-aliases-valid.s

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