[PATCH] D76619: AMDGPU/GlobalISel: Round up image operations with 5, 6 or 7 addresses

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: nhaehnle, kerbowa, foad.
Herald added subscribers: hiraditya, t-tye, tpr, dstuttard, rovka, yaxunl, wdng, jvesely, kzhuravl.

The instruction definitions are missing for these register types, so
round up to 8 like the DAG.


https://reviews.llvm.org/D76619

Files:
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D76619.252063.patch
Type: text/x-patch
Size: 11834 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200323/4b8207d4/attachment.bin>