[PATCH] D71767: [POC][SVE] Allow code generation for fixed length vectorised loops [Patch 2/2].

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally added a comment.

Ah, ok. So you wouldn't see fixed-width vector arguments since the vectorizers works at the loop/block/etc level. That's what I misunderstood.

We have a pre-IR vectorizer and vectorize lib calls, so our needs are a little askew.

What about a scheme where we make the fixed-width vector types proper subregs of the scalable types? That way we can add the fixed-width types to the calling conventions and register classes. Would that be of interest you?

It would be similar to X86's XMM->YMM->ZMM registers (i.e. 128b->256b->512b), except that all of SVE's sub-registers would print the same register name. it's a little hacky, but might polish up ok.

> I'll see about resolving the lack of tests albeit at this stage using pass by reference rather than value.

Thanks, but I'm fine without them for now. Up to you...


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