[PATCH] D76356: [AMDGPU] Introduce more scratch registers in the ABI.

[Tony Tye via Phabricator via llvm-commits]

t-tye added inline comments.


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Comment at: llvm/docs/AMDGPUUsage.rst:8710
+    * All SGPR registers except the clobbered registers of SGPR4-31.
+    * VGPR36-39
+      VGPR44-47
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arsenm wrote:
> t-tye wrote:
> > arsenm wrote:
> > > A description of why it's split this way may be helpful
> > Is the striping being picked at 4 VGPRs to match the hardware VGPR allocation granularity (4 for <=GFX9 and 8 for >=GFX10)? How does this stripping impact register file fragmentation? What is the impact of objects being promoted to registers that are larger than 4 VGPRs?
> These aren't used for argument passing, so there's no concept of objects to consider
Also this is an ABI breaking change (as is the change for the handling of the wave scratch offset) so should the EI_ABIVERSION for each EI_OSABI in the ELF header be bumped? My thinking is no since AMD has not yet started to support isa level linking nor function pointers so this change cannot affect any existing programs.


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  https://reviews.llvm.org/D76356/new/

https://reviews.llvm.org/D76356