[llvm] 56122fc - [PowerPC][AIX][NFC] Extend the test coverage of ByVal args.
Sean Fertile via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 20 09:20:11 PDT 2020
Author: Sean Fertile
Date: 2020-03-20T12:19:08-04:00
New Revision: 56122fcd641ae71de662575b0272994ef3a942b1
URL: https://github.com/llvm/llvm-project/commit/56122fcd641ae71de662575b0272994ef3a942b1
DIFF: https://github.com/llvm/llvm-project/commit/56122fcd641ae71de662575b0272994ef3a942b1.diff
LOG: [PowerPC][AIX][NFC] Extend the test coverage of ByVal args.
Adds/changes some types in the ByVal cc test so that they aren't all
structs of arrays of bytes, and adds testing for passing multiple
ByVal arguments.
Added:
Modified:
llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
index 45f19676c992..55713dfc70e6 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
@@ -110,7 +110,7 @@ declare void @test_byval_2Byte(%struct.S2* byval(%struct.S2) align 1)
; ASM64-NEXT: nop
; ASM64-NEXT: addi 1, 1, 112
-%struct.S3 = type { [3 x i8] }
+%struct.S3 = type <{ i8, i16 }>
@gS3 = external global %struct.S3, align 1
@@ -167,46 +167,55 @@ declare void @test_byval_3Byte(%struct.S3* byval(%struct.S3) align 1)
; ASM64-NEXT: nop
%struct.S4 = type { [4 x i8] }
+%struct.S4A = type { i32 }
@gS4 = external global %struct.S4, align 1
define void @call_test_byval_4Byte() {
entry:
%s0 = alloca %struct.S0, align 8
- call void @test_byval_4Byte(%struct.S4* byval(%struct.S4) align 1 @gS4, %struct.S0* byval(%struct.S0) align 1 %s0)
+ %s4a = alloca %struct.S4A, align 4
+ call void @test_byval_4Byte(%struct.S4* byval(%struct.S4) align 1 @gS4, %struct.S0* byval(%struct.S0) align 1 %s0, %struct.S4A* byval(%struct.S4A) align 4 %s4a)
ret void
}
-declare void @test_byval_4Byte(%struct.S4* byval(%struct.S4) align 1, %struct.S0* byval(%struct.S0) align 1)
+declare void @test_byval_4Byte(%struct.S4* byval(%struct.S4) align 1, %struct.S0* byval(%struct.S0) align 1, %struct.S4A* byval(%struct.S4A) align 4)
; CHECK-LABEL: name: call_test_byval_4Byte{{.*}}
; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: renamable $r[[REG:[0-9]+]] = LWZtoc @gS4, $r2 :: (load 4 from got)
-; 32BIT-NEXT: renamable $r3 = LWZ 0, killed renamable $r[[REG]] :: (load 4)
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_4Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
+; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REG]] :: (load 4)
+; 32BIT-DAG: renamable $r4 = LWZ 0, %stack.1.s4a :: (load 4 from %stack.1.s4a, align 8)
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_4Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_byval_4Byte:
-; ASM32: stwu 1, -64(1)
+; ASM32: stwu 1, -80(1)
; ASM32-NEXT: lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
-; ASM32-NEXT: lwz 3, 0([[REG]])
+; ASM32-DAG: lwz 3, 0([[REG]])
+; ASM32-DAG: lwz 4, 64(1)
; ASM32-NEXT: bl .test_byval_4Byte
; ASM32-NEXT: nop
-; ASM32-NEXT: addi 1, 1, 64
+; ASM32-NEXT: addi 1, 1, 80
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @gS4, $x2 :: (load 8 from got)
-; 64BIT-NEXT: renamable $x3 = LWZ8 0, killed renamable $x[[REG]] :: (load 4)
-; 64BIT-NEXT: renamable $x3 = RLDICR killed renamable $x3, 32, 31
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_4Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS4, $x2 :: (load 8 from got)
+; 64BIT-DAG: renamable $x[[LD1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
+; 64BIT-DAG: renamable $x[[LD2:[0-9]+]] = LWZ8 0, %stack.1.s4a :: (load 4 from %stack.1.s4a, align 8)
+; 64BIT-DAG: renamable $x3 = RLDICR killed renamable $x[[LD1]], 32, 31
+; 64BIT-DAG: renamable $x4 = RLDICR killed renamable $x[[LD2]], 32, 31
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_4Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; ASM64: stdu 1, -128(1)
-; ASM64-NEXT: ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
-; ASM64-NEXT: lwz 3, 0([[REG]])
-; ASM64-NEXT: sldi 3, 3, 32
+; ASM64-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-DAG: lwz [[LD1:[0-9]+]], 0([[REGADDR]])
+; ASM64-DAG: lwz [[LD2:[0-9]+]], 112(1)
+; ASM64-DAG: sldi 3, [[LD1]], 32
+; ASM64-DAG: sldi 4, [[LD2]], 32
; ASM64-NEXT: bl .test_byval_4Byte
; ASM64-NEXT: nop
; ASM64-NEXT: addi 1, 1, 128
+
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