[PATCH] D76238: [SveEmitter] Implement builtins for contiguous loads/stores

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen marked 4 inline comments as done.
sdesmalen added inline comments.


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Comment at: clang/include/clang/Basic/arm_sve.td:128
 def SVLD1   : MInst<"svld1[_{2}]", "dPc", "csilUcUsUiUlhfd", [IsLoad]>;
+def SVLD1SB : MInst<"svld1sb_{d}", "dPS", "silUsUiUl",       [IsLoad],              MemEltTyInt8>;
+def SVLD1UB : MInst<"svld1ub_{d}", "dPW", "silUsUiUl",       [IsLoad, IsZxtReturn], MemEltTyInt8>;
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SjoerdMeijer wrote:
> nit: don't think we have a coding style for tablegen, but it is exceeding 80 characters, even making this on phabricator a bit difficult to read, perhaps you can reshuffle this a bit.
I gave it a try to avoid these long lines, but found that this made the .td file a lot less readable. If you don't have a strong opinion on this, I'd prefer to keep it as-is.


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  https://reviews.llvm.org/D76238/new/

https://reviews.llvm.org/D76238