[PATCH] D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

In D65649#1931064 <https://reviews.llvm.org/D65649#1931064>, @simoncook wrote:

> This is starting to look good. I've checked all the encodings, and other than c.zext.w having the wrong value all the encodings are right.
>
> One thing I would consider is to make reviewing/future changes easier, I would define all the instructions in the order they appear in the Chapter 2.11 Opcode Encodings tables. This way, it will be easier to see for future revisions what has changed and make sure the encodings are up to date. This might end up with a few more `let Predicates = ` directives, but we can rearrange and tidy this up when it is all ratified.


Strong +1 on this. Throughout the RISC-V backend we order the instruction definitions to match the order in the ISA manual, with codegen patterns listed separately in a more meaningful order. As Simon say, it can lead to a few more `Predicates` directives needed, but makes cross-referencing vs the spec _much_ easier.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65649/new/

https://reviews.llvm.org/D65649