[PATCH] D76398: [X86] Enable prefix padding w/target specific padding amount

Wed Mar 18 17:24:10 PDT 2020

reames created this revision.
reames added reviewers: skan, annita.zhang, LuoYuanke, craig.topper.
Herald added subscribers: dantrushin, bollu, hiraditya, mcrosier.
Herald added a project: LLVM.
reames planned changes to this revision.
reames added a comment.

I need to restructure this.  As I noted over in https://reviews.llvm.org/D76176, we have a problem for the assembler use case w/inserting prefixes between previous data encoded prefixes and the instruction.  This isn't relevant for the compiler (since we have the suppression mechanism), but we need to structure this such that only the compiler enables this feature.  I'm very unhappy about how ugly that is, but I don't see a way around it.

This change does two related things.

First, it defines the maximum number of prefixes safe to use for padding in a target specific way.  As noted in the comments, different processor generations behave very differently w.r.t. redundant prefixes.  Some processors - mostly, but not entirely older ones - encounter serious stalls if too many prefixes are used.

Second, it enables prefix padding of relaxable instructions by default.

Note that while I'm posting this for review - and I would appreciate real review, in particular of the target specific parts - I am not planning on landing it for at least a week.  I'm waiting on results from a fuzzer run to see if we smoke out any correctness issues before we enable this broadly.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76398

Files:
  llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
  llvm/test/MC/X86/align-branch-64-hardcode.s
  llvm/test/MC/X86/align-branch-64-prefix.s

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