[PATCH] D76387: [AMDGPU] Resue register during frame index elimination

[Austin Kerbow via Phabricator via llvm-commits]

kerbowa created this revision.
kerbowa added a reviewer: arsenm.
Herald added subscribers: llvm-commits, arphaman, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, qcolombet.
Herald added a project: LLVM.

If there were no free VGPRs we would need two emergency spill slots for register
scavenging during PEI/frame index elimination. Reuse 'ResultReg' for scale
calculation so that only one spill is needed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76387

Files:
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
  llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
  llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
  llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir

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