[llvm] e009fad - [PowerPC] Remove UB from PPCInstrInfo when handling rotates fed by constants

[Nemanja Ivanovic via llvm-commits]

Author: Nemanja Ivanovic
Date: 2020-03-18T13:40:39-05:00
New Revision: e009fad342cedb8ed3ddc7c4c6e21d6d965abbbc

URL: https://github.com/llvm/llvm-project/commit/e009fad342cedb8ed3ddc7c4c6e21d6d965abbbc
DIFF: https://github.com/llvm/llvm-project/commit/e009fad342cedb8ed3ddc7c4c6e21d6d965abbbc.diff

LOG: [PowerPC] Remove UB from PPCInstrInfo when handling rotates fed by constants

As pointed out in https://bugs.llvm.org/show_bug.cgi?id=45232 this code can
end up shifting a 64-bit unsigned value left by 64 bits. Althought this works
as expected on some platforms it is definitely UB. This patch removes the UB
and adds the associated test case.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=45232

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
    llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 1b3c52b4edf0..f7a68dd16229 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2879,7 +2879,7 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
     APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec) ? 64 : 32,
                 SExtImm, true);
     InVal = InVal.rotl(SH);
-    uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
+    uint64_t Mask = MB == 0 ? -1LLU : (1LLU << (63 - MB + 1)) - 1;
     InVal &= Mask;
     // Can't replace negative values with an LI as that will sign-extend
     // and not clear the left bits. If we're setting the CR bit, we will use

diff  --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
index df5b040b5dcd..c922312eae12 100644
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
@@ -550,6 +550,14 @@
     ret i64 %and
   }
   
+  ; Function Attrs: norecurse nounwind readnone
+  define i64 @testRLDICL_MB0(i64 %a) local_unnamed_addr #0 {
+  entry:
+    %shr = lshr i64 %a, 11
+    %and = and i64 %shr, 16777215
+    ret i64 %and
+  }
+  
   ; Function Attrs: norecurse nounwind readnone
   define i64 @testRLDICL_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
@@ -3882,6 +3890,52 @@ body:             |
     $x3 = COPY %1
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
+...
+---
+name:            testRLDICL_MB0
+# CHECK-ALL: name: testRLDICL_MB0
+alignment:       16
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:       
+  - { id: 0, class: g8rc, preferred-register: '' }
+  - { id: 1, class: g8rc, preferred-register: '' }
+liveins:         
+  - { reg: '$x3', virtual-reg: '%0' }
+frameInfo:       
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      
+stack:           
+constants:       
+body:             |
+  bb.0.entry:
+    liveins: $x3
+  
+    %0 = LI8 32
+    %1 = RLDICL %0, 60, 0
+    ; CHECK: LI8 2
+    ; CHECK-LATE: li 3, 2
+    $x3 = COPY %1
+    BLR8 implicit $lr8, implicit $rm, implicit $x3
+
 ...
 ---
 name:            testRLDICL_rec