[PATCH] D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions.

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill added a comment.

All looks good apart from some test nitpicks. Also add more reviewers



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Comment at: llvm/test/CodeGen/RISCV/rv32Zbb.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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This comment is not the case for these files anymore right?


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Comment at: llvm/test/CodeGen/RISCV/rv64Zbs.ll:9
+
+define i64 @_sbset(i64 %a, i64 %b) nounwind {
+; RV64I-NOT:    sbset a0, a0, a1
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I'm not certain what the underscore is for, assuming it's to avoid clashing with LLVM intrinsics? If so shouldn't all LLVM intrinsics which cause a clash have a lowering?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67348/new/

https://reviews.llvm.org/D67348