[llvm] be9e3d9 - [InstCombine] reduce demand-limited bool math to logic, part 2

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2020-03-17T15:18:18-04:00
New Revision: be9e3d9416571499adb15f3f943b8f5cb3089f1a

URL: https://github.com/llvm/llvm-project/commit/be9e3d9416571499adb15f3f943b8f5cb3089f1a
DIFF: https://github.com/llvm/llvm-project/commit/be9e3d9416571499adb15f3f943b8f5cb3089f1a.diff

LOG: [InstCombine] reduce demand-limited bool math to logic, part 2

Follow-on suggested in:
D75961

Added: 
    

Modified: 
    llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
    llvm/test/Transforms/InstCombine/add.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index 59ed96a0257a..aa5d33ce8ac8 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -456,22 +456,39 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
   case Instruction::Add:
     if ((DemandedMask & 1) == 0) {
       // If we do not need the low bit, try to convert bool math to logic:
-      //   add iN (zext i1 X), (sext i1 Y) --> sext (~X & Y) to iN
-      // Truth table for inputs and output signbits:
-      //       X:0 | X:1
-      //      ----------
-      // Y:0  |  0 | 0 |
-      // Y:1  | -1 | 0 |
-      //      ----------
+      // add iN (zext i1 X), (sext i1 Y) --> sext (~X & Y) to iN
       Value *X, *Y;
       if (match(I, m_c_Add(m_OneUse(m_ZExt(m_Value(X))),
                            m_OneUse(m_SExt(m_Value(Y))))) &&
           X->getType()->isIntOrIntVectorTy(1) && X->getType() == Y->getType()) {
+        // Truth table for inputs and output signbits:
+        //       X:0 | X:1
+        //      ----------
+        // Y:0  |  0 | 0 |
+        // Y:1  | -1 | 0 |
+        //      ----------
         IRBuilderBase::InsertPointGuard Guard(Builder);
         Builder.SetInsertPoint(I);
         Value *AndNot = Builder.CreateAnd(Builder.CreateNot(X), Y);
         return Builder.CreateSExt(AndNot, VTy);
       }
+
+      // add iN (sext i1 X), (sext i1 Y) --> sext (X | Y) to iN
+      // TODO: Relax the one-use checks because we are removing an instruction?
+      if (match(I, m_Add(m_OneUse(m_SExt(m_Value(X))),
+                         m_OneUse(m_SExt(m_Value(Y))))) &&
+          X->getType()->isIntOrIntVectorTy(1) && X->getType() == Y->getType()) {
+        // Truth table for inputs and output signbits:
+        //       X:0 | X:1
+        //      -----------
+        // Y:0  | -1 | -1 |
+        // Y:1  | -1 |  0 |
+        //      -----------
+        IRBuilderBase::InsertPointGuard Guard(Builder);
+        Builder.SetInsertPoint(I);
+        Value *Or = Builder.CreateOr(X, Y);
+        return Builder.CreateSExt(Or, VTy);
+      }
     }
     LLVM_FALLTHROUGH;
   case Instruction::Sub: {

diff  --git a/llvm/test/Transforms/InstCombine/add.ll b/llvm/test/Transforms/InstCombine/add.ll
index 3ae0d50027f0..24fcae5cd870 100644
--- a/llvm/test/Transforms/InstCombine/add.ll
+++ b/llvm/test/Transforms/InstCombine/add.ll
@@ -1184,10 +1184,8 @@ define i32 @lshr_add_use2(i1 %x, i1 %y, i32* %p) {
 
 define i32 @lshr_add_sexts(i1 %x, i1 %y) {
 ; CHECK-LABEL: @lshr_add_sexts(
-; CHECK-NEXT:    [[XS:%.*]] = sext i1 [[X:%.*]] to i32
-; CHECK-NEXT:    [[YS:%.*]] = sext i1 [[Y:%.*]] to i32
-; CHECK-NEXT:    [[SUB:%.*]] = add nsw i32 [[XS]], [[YS]]
-; CHECK-NEXT:    [[R:%.*]] = lshr i32 [[SUB]], 31
+; CHECK-NEXT:    [[TMP1:%.*]] = or i1 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = zext i1 [[TMP1]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %xs = sext i1 %x to i32
@@ -1199,10 +1197,8 @@ define i32 @lshr_add_sexts(i1 %x, i1 %y) {
 
 define i5 @and_add_sexts(i1 %x, i1 %y) {
 ; CHECK-LABEL: @and_add_sexts(
-; CHECK-NEXT:    [[XS:%.*]] = sext i1 [[X:%.*]] to i5
-; CHECK-NEXT:    [[YS:%.*]] = sext i1 [[Y:%.*]] to i5
-; CHECK-NEXT:    [[SUB:%.*]] = add nsw i5 [[XS]], [[YS]]
-; CHECK-NEXT:    [[R:%.*]] = and i5 [[SUB]], -2
+; CHECK-NEXT:    [[TMP1:%.*]] = or i1 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP1]], i5 -2, i5 0
 ; CHECK-NEXT:    ret i5 [[R]]
 ;
   %xs = sext i1 %x to i5
@@ -1214,11 +1210,9 @@ define i5 @and_add_sexts(i1 %x, i1 %y) {
 
 define <2 x i8> @ashr_add_sexts(<2 x i1> %x, <2 x i1> %y) {
 ; CHECK-LABEL: @ashr_add_sexts(
-; CHECK-NEXT:    [[XS:%.*]] = sext <2 x i1> [[X:%.*]] to <2 x i8>
-; CHECK-NEXT:    [[YS:%.*]] = sext <2 x i1> [[Y:%.*]] to <2 x i8>
-; CHECK-NEXT:    [[SUB:%.*]] = add nsw <2 x i8> [[YS]], [[XS]]
-; CHECK-NEXT:    [[R:%.*]] = ashr <2 x i8> [[SUB]], <i8 1, i8 1>
-; CHECK-NEXT:    ret <2 x i8> [[R]]
+; CHECK-NEXT:    [[TMP1:%.*]] = or <2 x i1> [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sext <2 x i1> [[TMP1]] to <2 x i8>
+; CHECK-NEXT:    ret <2 x i8> [[TMP2]]
 ;
   %xs = sext <2 x i1> %x to <2 x i8>
   %ys = sext <2 x i1> %y to <2 x i8>
@@ -1229,12 +1223,8 @@ define <2 x i8> @ashr_add_sexts(<2 x i1> %x, <2 x i1> %y) {
 
 define i32 @cmp_math_sexts(i32 %x, i32 %y) {
 ; CHECK-LABEL: @cmp_math_sexts(
-; CHECK-NEXT:    [[GT:%.*]] = icmp ugt i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[LT:%.*]] = icmp ult i32 [[X]], [[Y]]
-; CHECK-NEXT:    [[XZ:%.*]] = sext i1 [[GT]] to i32
-; CHECK-NEXT:    [[TMP1:%.*]] = sext i1 [[LT]] to i32
-; CHECK-NEXT:    [[S:%.*]] = add nsw i32 [[XZ]], [[TMP1]]
-; CHECK-NEXT:    [[R:%.*]] = lshr i32 [[S]], 31
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = zext i1 [[TMP1]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %gt = icmp ugt i32 %x, %y