[llvm] e0ab0e6 - [MIPS] Implement PUL.PS and PUU.PS instructions
Simon Atanasyan via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 15 23:40:37 PDT 2020
Author: Simon Atanasyan
Date: 2020-03-16T09:39:47+03:00
New Revision: e0ab0e6a281f75e33090ed7f382a5f5e553fb393
URL: https://github.com/llvm/llvm-project/commit/e0ab0e6a281f75e33090ed7f382a5f5e553fb393
DIFF: https://github.com/llvm/llvm-project/commit/e0ab0e6a281f75e33090ed7f382a5f5e553fb393.diff
LOG: [MIPS] Implement PUL.PS and PUU.PS instructions
Patch by Michael Roe.
Differential Revision: https://reviews.llvm.org/D75812
Added:
Modified:
llvm/lib/Target/Mips/MipsInstrFPU.td
llvm/lib/Target/Mips/MipsScheduleGeneric.td
llvm/lib/Target/Mips/MipsScheduleP5600.td
llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s
llvm/test/MC/Mips/mips1/invalid-mips5.s
llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s
llvm/test/MC/Mips/mips2/invalid-mips5.s
llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s
llvm/test/MC/Mips/mips3/invalid-mips5.s
llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s
llvm/test/MC/Mips/mips4/invalid-mips5.s
llvm/test/MC/Mips/mips64r2/valid-xfail.s
llvm/test/MC/Mips/mips64r2/valid.s
llvm/test/MC/Mips/mips64r3/valid-xfail.s
llvm/test/MC/Mips/mips64r3/valid.s
llvm/test/MC/Mips/mips64r5/valid-xfail.s
llvm/test/MC/Mips/mips64r5/valid.s
llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s
llvm/test/MC/Mips/mips64r6/invalid-mips5.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td
index 4ad0665d1823..63ccf3016cf3 100644
--- a/llvm/lib/Target/Mips/MipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MipsInstrFPU.td
@@ -456,6 +456,12 @@ let DecoderNamespace = "MipsFP64" in {
def PLU_PS64 : ADDS_FT<"plu.ps", FGR64Opnd, II_CVT, 0>,
ADDS_FM<0x2D, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
+ def PUL_PS64 : ADDS_FT<"pul.ps", FGR64Opnd, II_CVT, 0>,
+ ADDS_FM<0x2E, 22>,
+ ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
+ def PUU_PS64 : ADDS_FT<"puu.ps", FGR64Opnd, II_CVT, 0>,
+ ADDS_FM<0x2F, 22>,
+ ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
def CVT_S_PU64 : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x20, 22>,
diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
index faccb37c2361..10cae1bd4c48 100644
--- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td
+++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
@@ -832,7 +832,7 @@ def : InstRW<[GenericWriteFPUL], (instrs CEIL_L_D64, CEIL_L_S, CEIL_W_D32,
FLOOR_W_D64, FLOOR_W_S, FMUL_D32, FMUL_D64,
MADD_D32, MADD_D64, MSUB_D32, MSUB_D64,
NMADD_D32, NMADD_D64, NMSUB_D32, NMSUB_D64,
- PLL_PS64, PLU_PS64,
+ PLL_PS64, PLU_PS64, PUL_PS64, PUU_PS64,
ROUND_L_D64, ROUND_L_S, ROUND_W_D32,
ROUND_W_D64, ROUND_W_S, TRUNC_L_D64,
TRUNC_L_S, TRUNC_W_D32, TRUNC_W_D64,
diff --git a/llvm/lib/Target/Mips/MipsScheduleP5600.td b/llvm/lib/Target/Mips/MipsScheduleP5600.td
index 7331917baa25..cc57e8daa21b 100644
--- a/llvm/lib/Target/Mips/MipsScheduleP5600.td
+++ b/llvm/lib/Target/Mips/MipsScheduleP5600.td
@@ -457,7 +457,7 @@ def : InstRW<[P5600WriteFPUL], (instrs CVT_PS_S64, CVT_S_PL64, CVT_S_PU64)>;
def : InstRW<[P5600WriteFPUL], (instregex "^C_[A-Z]+_(S|D32|D64)$")>;
def : InstRW<[P5600WriteFPUL], (instregex "^FCMP_(S32|D32|D64)$")>;
def : InstRW<[P5600WriteFPUL], (instregex "^PseudoCVT_(S|D32|D64)_(L|W)$")>;
-def : InstRW<[P5600WriteFPUL], (instrs PLL_PS64, PLU_PS64)>;
+def : InstRW<[P5600WriteFPUL], (instrs PLL_PS64, PLU_PS64, PUL_PS64, PUU_PS64)>;
// div.[ds], div.ps
def : InstRW<[P5600WriteFPUDivS], (instrs FDIV_S)>;
diff --git a/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s
index 7cdbd89f1d4f..cb590a7df5cf 100644
--- a/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s
+++ b/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s
@@ -36,8 +36,6 @@
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
c.f.s $fcc4, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
diff --git a/llvm/test/MC/Mips/mips1/invalid-mips5.s b/llvm/test/MC/Mips/mips1/invalid-mips5.s
index d309385c3d8e..bfce1e55b4ba 100644
--- a/llvm/test/MC/Mips/mips1/invalid-mips5.s
+++ b/llvm/test/MC/Mips/mips1/invalid-mips5.s
@@ -73,6 +73,8 @@
movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s
index 199f2ce3891d..0bd2ef65489b 100644
--- a/llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s
+++ b/llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s
@@ -36,6 +36,4 @@
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
diff --git a/llvm/test/MC/Mips/mips2/invalid-mips5.s b/llvm/test/MC/Mips/mips2/invalid-mips5.s
index 7485f6dcb788..ad5f2b583f06 100644
--- a/llvm/test/MC/Mips/mips2/invalid-mips5.s
+++ b/llvm/test/MC/Mips/mips2/invalid-mips5.s
@@ -69,6 +69,8 @@
movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s
index 43b9bfdf06d4..19711ba05f28 100644
--- a/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s
+++ b/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s
@@ -36,7 +36,5 @@
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
diff --git a/llvm/test/MC/Mips/mips3/invalid-mips5.s b/llvm/test/MC/Mips/mips3/invalid-mips5.s
index 15928d59a7d5..31896e0392e6 100644
--- a/llvm/test/MC/Mips/mips3/invalid-mips5.s
+++ b/llvm/test/MC/Mips/mips3/invalid-mips5.s
@@ -32,6 +32,8 @@
movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sdxc1 $f11,$a6($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s
index c7a07bf286b2..1a2f020cb9de 100644
--- a/llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s
+++ b/llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s
@@ -36,6 +36,4 @@
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
diff --git a/llvm/test/MC/Mips/mips4/invalid-mips5.s b/llvm/test/MC/Mips/mips4/invalid-mips5.s
index 04526fc1e153..2dc7681bd038 100644
--- a/llvm/test/MC/Mips/mips4/invalid-mips5.s
+++ b/llvm/test/MC/Mips/mips4/invalid-mips5.s
@@ -11,4 +11,6 @@
cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
\ No newline at end of file
+ plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/mips64r2/valid-xfail.s b/llvm/test/MC/Mips/mips64r2/valid-xfail.s
index f043b6b934ef..7c7ed5274828 100644
--- a/llvm/test/MC/Mips/mips64r2/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips64r2/valid-xfail.s
@@ -65,8 +65,6 @@
nmsub.ps $f6,$f12,$f14,$f17
preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15
- pul.ps $f9,$f30,$f26
- puu.ps $f24,$f9,$f2
rdpgpr $s3,$9
rorv $13,$a3,$s5
sbe $s7,33($s1)
diff --git a/llvm/test/MC/Mips/mips64r2/valid.s b/llvm/test/MC/Mips/mips64r2/valid.s
index c093102d7593..c7696ba455e4 100644
--- a/llvm/test/MC/Mips/mips64r2/valid.s
+++ b/llvm/test/MC/Mips/mips64r2/valid.s
@@ -294,6 +294,12 @@ a:
plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad]
# CHECK: # <MCInst #{{[0-9]+}} PLU_PS64
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
+ pul.ps $f9,$f30,$f26 # CHECK: pul.ps $f9, $f30, $f26 # encoding: [0x46,0xda,0xf2,0x6e]
+ # CHECK: # <MCInst #{{[0-9]+}} PUL_PS64
+
+ puu.ps $f24,$f9,$f2 # CHECK: puu.ps $f24, $f9, $f2 # encoding: [0x46,0xc2,0x4e,0x2f]
+ # CHECK: # <MCInst #{{[0-9]+}} PUU_PS64
+
# FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push
diff --git a/llvm/test/MC/Mips/mips64r3/valid-xfail.s b/llvm/test/MC/Mips/mips64r3/valid-xfail.s
index 319db7d6a83e..4c368e5f12e2 100644
--- a/llvm/test/MC/Mips/mips64r3/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips64r3/valid-xfail.s
@@ -68,8 +68,6 @@
nmsub.ps $f6,$f12,$f14,$f17
preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15
- pul.ps $f9,$f30,$f26
- puu.ps $f24,$f9,$f2
rdpgpr $s3,$9
rorv $13,$a3,$s5
sbe $s7,33($s1)
diff --git a/llvm/test/MC/Mips/mips64r3/valid.s b/llvm/test/MC/Mips/mips64r3/valid.s
index 84c2c443f786..76c6f13bc21a 100644
--- a/llvm/test/MC/Mips/mips64r3/valid.s
+++ b/llvm/test/MC/Mips/mips64r3/valid.s
@@ -288,6 +288,10 @@ a:
plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad]
# CHECK: # <MCInst #{{[0-9]+}} PLU_PS64
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
+ pul.ps $f9,$f30,$f26 # CHECK: pul.ps $f9, $f30, $f26 # encoding: [0x46,0xda,0xf2,0x6e]
+ # CHECK: # <MCInst #{{[0-9]+}} PUL_PS64
+ puu.ps $f24,$f9,$f2 # CHECK: puu.ps $f24, $f9, $f2 # encoding: [0x46,0xc2,0x4e,0x2f]
+ # CHECK: # <MCInst #{{[0-9]+}} PUU_PS64
# FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push
diff --git a/llvm/test/MC/Mips/mips64r5/valid-xfail.s b/llvm/test/MC/Mips/mips64r5/valid-xfail.s
index 23805c5f0f86..d75f2b2bb930 100644
--- a/llvm/test/MC/Mips/mips64r5/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips64r5/valid-xfail.s
@@ -68,8 +68,6 @@
nmsub.ps $f6,$f12,$f14,$f17
preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15
- pul.ps $f9,$f30,$f26
- puu.ps $f24,$f9,$f2
rdpgpr $s3,$9
rorv $13,$a3,$s5
sbe $s7,33($s1)
diff --git a/llvm/test/MC/Mips/mips64r5/valid.s b/llvm/test/MC/Mips/mips64r5/valid.s
index 13069d08992d..540a832146f4 100644
--- a/llvm/test/MC/Mips/mips64r5/valid.s
+++ b/llvm/test/MC/Mips/mips64r5/valid.s
@@ -290,6 +290,10 @@ a:
plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad]
# CHECK: # <MCInst #{{[0-9]+}} PLU_PS64
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
+ pul.ps $f9,$f30,$f26 # CHECK: pul.ps $f9, $f30, $f26 # encoding: [0x46,0xda,0xf2,0x6e]
+ # CHECK: # <MCInst #{{[0-9]+}} PUL_PS64
+ puu.ps $f24,$f9,$f2 # CHECK: puu.ps $f24, $f9, $f2 # encoding: [0x46,0xc2,0x4e,0x2f]
+ # CHECK: # <MCInst #{{[0-9]+}} PUU_PS64
# FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push
diff --git a/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s
index 0758164d0c77..8dc8c0b47d00 100644
--- a/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s
+++ b/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s
@@ -40,6 +40,4 @@
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
- puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
diff --git a/llvm/test/MC/Mips/mips64r6/invalid-mips5.s b/llvm/test/MC/Mips/mips64r6/invalid-mips5.s
index e7fd99a6b05b..a78f75b9c6fd 100644
--- a/llvm/test/MC/Mips/mips64r6/invalid-mips5.s
+++ b/llvm/test/MC/Mips/mips64r6/invalid-mips5.s
@@ -9,4 +9,8 @@
bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
suxc1 $f12,$k1($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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