[PATCH] D70771: [PowerPC] Replace the PPCISD:: SExtVElems with ISD::SIGN_EXTEND_INREG to leverage the combine rules

qshanz via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Mar 13 00:50:50 PDT 2020


This revision was automatically updated to reflect the committed changes.
Closed by commit rGd0fb34dc0967: [PowerPC] Replace the PPCISD:: SExtVElems with ISD::SIGN_EXTEND_INREG to… (authored by steven.zhang).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70771/new/

https://reviews.llvm.org/D70771

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td

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