[llvm] 1ba3d26 - [PowerPC][NFC] Rename instruction formats in PPCInstrPrefix.td
Amy Kwan via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 12 22:50:37 PDT 2020
Author: Amy Kwan
Date: 2020-03-13T00:50:08-05:00
New Revision: 1ba3d2639d1c489a3876f72d822446c10fca0a23
URL: https://github.com/llvm/llvm-project/commit/1ba3d2639d1c489a3876f72d822446c10fca0a23
DIFF: https://github.com/llvm/llvm-project/commit/1ba3d2639d1c489a3876f72d822446c10fca0a23.diff
LOG: [PowerPC][NFC] Rename instruction formats in PPCInstrPrefix.td
This patch renames some of the instruction formats within PPCInstrPrefix.td to
adopt a more uniform naming convention. It also adds the naming convention
extension, `_MEM` to indicate instruction formats for memory ops.
Differential Revision: https://reviews.llvm.org/D75819
Added:
Modified:
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index f4e2f74236b1..d423f6f5f164 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -43,8 +43,8 @@ class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
string BaseName = "";
}
-class MLS_DForm_R_D34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
- InstrItinClass itin, list<dag> pattern>
+class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
: PI<1, opcode, OOL, IOL, asmstr, itin> {
bits<5> FRS;
bits<39> D_RA;
@@ -86,8 +86,8 @@ class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
let Inst{48-63} = SI{15-0};
}
-class MLS_DForm2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
- InstrItinClass itin, list<dag> pattern>
+class MLS_DForm_SI34_RT5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
: PI<1, opcode, OOL, IOL, asmstr, itin> {
bits<5> RT;
bits<34> SI;
@@ -116,8 +116,8 @@ multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
!strconcat(asmstr, ", 1"), itin, []>, isPCRel;
}
-class 8LS_DForm_R_D34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
- InstrItinClass itin, list<dag> pattern>
+class 8LS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
: PI<1, opcode, OOL, IOL, asmstr, itin> {
bits<5> RT;
bits<39> D_RA;
@@ -138,8 +138,8 @@ class 8LS_DForm_R_D34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
// 8LS:D-Form: [ 1 0 0 // R // d0
// PO TX T RA d1 ]
-class 8LS_DForm_R_D34_XT6_RA5<bits<5> opcode, dag OOL, dag IOL, string asmstr,
- InstrItinClass itin, list<dag> pattern>
+class 8LS_DForm_R_SI34_XT6_RA5<bits<5> opcode, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
: PI<1, { opcode, ? }, OOL, IOL, asmstr, itin> {
bits<6> XT;
bits<39> D_RA;
@@ -161,33 +161,33 @@ class 8LS_DForm_R_D34_XT6_RA5<bits<5> opcode, dag OOL, dag IOL, string asmstr,
let Inst{48-63} = D_RA{15-0}; // d1
}
-multiclass MLS_DForm_R_D34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
- dag PCRel_IOL, string asmstr,
- InstrItinClass itin> {
- def NAME : MLS_DForm_R_D34_RTA5<opcode, OOL, IOL,
- !strconcat(asmstr, ", 0"), itin, []>;
- def pc : MLS_DForm_R_D34_RTA5<opcode, OOL, PCRel_IOL,
- !strconcat(asmstr, ", 1"), itin, []>,
- isPCRel;
+multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
+ dag PCRel_IOL, string asmstr,
+ InstrItinClass itin> {
+ def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL,
+ !strconcat(asmstr, ", 0"), itin, []>;
+ def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL,
+ !strconcat(asmstr, ", 1"), itin, []>,
+ isPCRel;
}
-multiclass 8LS_DForm_R_D34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
- dag PCRel_IOL, string asmstr,
- InstrItinClass itin> {
- def NAME : 8LS_DForm_R_D34_RTA5<opcode, OOL, IOL,
- !strconcat(asmstr, ", 0"), itin, []>;
- def pc : 8LS_DForm_R_D34_RTA5<opcode, OOL, PCRel_IOL,
- !strconcat(asmstr, ", 1"), itin, []>, isPCRel;
+multiclass 8LS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
+ dag PCRel_IOL, string asmstr,
+ InstrItinClass itin> {
+ def NAME : 8LS_DForm_R_SI34_RTA5<opcode, OOL, IOL,
+ !strconcat(asmstr, ", 0"), itin, []>;
+ def pc : 8LS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL,
+ !strconcat(asmstr, ", 1"), itin, []>, isPCRel;
}
-multiclass 8LS_DForm_R_D34_XT6_RA5_p<bits<5> opcode, dag OOL, dag IOL,
- dag PCRel_IOL, string asmstr,
- InstrItinClass itin> {
- def NAME : 8LS_DForm_R_D34_XT6_RA5<opcode, OOL, IOL,
- !strconcat(asmstr, ", 0"), itin, []>;
- def pc : 8LS_DForm_R_D34_XT6_RA5<opcode, OOL, PCRel_IOL,
- !strconcat(asmstr, ", 1"), itin, []>,
- isPCRel;
+multiclass 8LS_DForm_R_SI34_XT6_RA5_p<bits<5> opcode, dag OOL, dag IOL,
+ dag PCRel_IOL, string asmstr,
+ InstrItinClass itin> {
+ def NAME : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, IOL,
+ !strconcat(asmstr, ", 0"), itin, []>;
+ def pc : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, PCRel_IOL,
+ !strconcat(asmstr, ", 1"), itin, []>,
+ isPCRel;
}
def PrefixInstrs : Predicate<"PPCSubTarget->hasPrefixInstrs()">;
@@ -199,9 +199,9 @@ let Predicates = [PrefixInstrs] in {
(ins immZero:$RA, s34imm:$SI),
"paddi $RT, $RA, $SI", IIC_LdStLFD>;
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
- def PLI8 : MLS_DForm2_r0<14, (outs g8rc:$RT),
- (ins s34imm:$SI),
- "pli $RT, $SI", IIC_IntSimple, []>;
+ def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
+ (ins s34imm:$SI),
+ "pli $RT, $SI", IIC_IntSimple, []>;
}
}
defm PADDI :
@@ -209,131 +209,131 @@ let Predicates = [PrefixInstrs] in {
(ins immZero:$RA, s34imm:$SI),
"paddi $RT, $RA, $SI", IIC_LdStLFD>;
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
- def PLI : MLS_DForm2_r0<14, (outs gprc:$RT),
- (ins s34imm:$SI),
- "pli $RT, $SI", IIC_IntSimple, []>;
+ def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
+ (ins s34imm:$SI),
+ "pli $RT, $SI", IIC_IntSimple, []>;
}
let mayLoad = 1, mayStore = 0 in {
defm PLXV :
- 8LS_DForm_R_D34_XT6_RA5_p<25, (outs vsrc:$XT), (ins memri34:$D_RA),
- (ins memri34_pcrel:$D_RA), "plxv $XT, $D_RA",
- IIC_LdStLFD>;
+ 8LS_DForm_R_SI34_XT6_RA5_p<25, (outs vsrc:$XT), (ins memri34:$D_RA),
+ (ins memri34_pcrel:$D_RA), "plxv $XT, $D_RA",
+ IIC_LdStLFD>;
defm PLFS :
- MLS_DForm_R_D34_RTA5_p<48, (outs f4rc:$FRT), (ins memri34:$D_RA),
- (ins memri34_pcrel:$D_RA), "plfs $FRT, $D_RA",
- IIC_LdStLFD>;
+ MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$FRT), (ins memri34:$D_RA),
+ (ins memri34_pcrel:$D_RA), "plfs $FRT, $D_RA",
+ IIC_LdStLFD>;
defm PLFD :
- MLS_DForm_R_D34_RTA5_p<50, (outs f8rc:$FRT), (ins memri34:$D_RA),
- (ins memri34_pcrel:$D_RA), "plfd $FRT, $D_RA",
- IIC_LdStLFD>;
+ MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$FRT), (ins memri34:$D_RA),
+ (ins memri34_pcrel:$D_RA), "plfd $FRT, $D_RA",
+ IIC_LdStLFD>;
defm PLXSSP :
- 8LS_DForm_R_D34_RTA5_p<43, (outs vfrc:$VRT), (ins memri34:$D_RA),
- (ins memri34_pcrel:$D_RA), "plxssp $VRT, $D_RA",
- IIC_LdStLFD>;
+ 8LS_DForm_R_SI34_RTA5_p<43, (outs vfrc:$VRT), (ins memri34:$D_RA),
+ (ins memri34_pcrel:$D_RA), "plxssp $VRT, $D_RA",
+ IIC_LdStLFD>;
defm PLXSD :
- 8LS_DForm_R_D34_RTA5_p<42, (outs vfrc:$VRT), (ins memri34:$D_RA),
- (ins memri34_pcrel:$D_RA), "plxsd $VRT, $D_RA",
- IIC_LdStLFD>;
+ 8LS_DForm_R_SI34_RTA5_p<42, (outs vfrc:$VRT), (ins memri34:$D_RA),
+ (ins memri34_pcrel:$D_RA), "plxsd $VRT, $D_RA",
+ IIC_LdStLFD>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm PLBZ8 :
- MLS_DForm_R_D34_RTA5_p<34, (outs g8rc:$RT), (ins memri34:$D_RA),
- (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA",
- IIC_LdStLFD>;
+ MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RT), (ins memri34:$D_RA),
+ (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA",
+ IIC_LdStLFD>;
defm PLHZ8 :
- MLS_DForm_R_D34_RTA5_p<40, (outs g8rc:$RT), (ins memri34:$D_RA),
- (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA",
- IIC_LdStLFD>;
+ MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RT), (ins memri34:$D_RA),
+ (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA",
+ IIC_LdStLFD>;
defm PLHA8 :
- MLS_DForm_R_D34_RTA5_p<42, (outs g8rc:$RT), (ins memri34:$D_RA),
- (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA",
- IIC_LdStLFD>;
+ MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RT), (ins memri34:$D_RA),
+ (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA",
+ IIC_LdStLFD>;
defm PLWA8 :
- 8LS_DForm_R_D34_RTA5_p<41, (outs g8rc:$RT), (ins memri34:$D_RA),
- (ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA",
- IIC_LdStLFD>;
+ 8LS_DForm_R_SI34_RTA5_p<41, (outs g8rc:$RT), (ins memri34:$D_RA),
+ (ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA",
+ IIC_LdStLFD>;
defm PLWZ8 :
- MLS_DForm_R_D34_RTA5_p<32, (outs g8rc:$RT), (ins memri34:$D_RA),
- (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA",
- IIC_LdStLFD>;
+ MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RT), (ins memri34:$D_RA),
+ (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA",
+ IIC_LdStLFD>;
}
defm PLBZ :
- MLS_DForm_R_D34_RTA5_p<34, (outs gprc:$RT), (ins memri34:$D_RA),
- (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA",
- IIC_LdStLFD>;
+ MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RT), (ins memri34:$D_RA),
+ (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA",
+ IIC_LdStLFD>;
defm PLHZ :
- MLS_DForm_R_D34_RTA5_p<40, (outs gprc:$RT), (ins memri34:$D_RA),
- (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA",
- IIC_LdStLFD>;
+ MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RT), (ins memri34:$D_RA),
+ (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA",
+ IIC_LdStLFD>;
defm PLHA :
- MLS_DForm_R_D34_RTA5_p<42, (outs gprc:$RT), (ins memri34:$D_RA),
- (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA",
- IIC_LdStLFD>;
+ MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RT), (ins memri34:$D_RA),
+ (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA",
+ IIC_LdStLFD>;
defm PLWZ :
- MLS_DForm_R_D34_RTA5_p<32, (outs gprc:$RT), (ins memri34:$D_RA),
- (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA",
- IIC_LdStLFD>;
+ MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RT), (ins memri34:$D_RA),
+ (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA",
+ IIC_LdStLFD>;
defm PLWA :
- 8LS_DForm_R_D34_RTA5_p<41, (outs gprc:$RT), (ins memri34:$D_RA),
- (ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA",
- IIC_LdStLFD>;
+ 8LS_DForm_R_SI34_RTA5_p<41, (outs gprc:$RT), (ins memri34:$D_RA),
+ (ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA",
+ IIC_LdStLFD>;
defm PLD :
- 8LS_DForm_R_D34_RTA5_p<57, (outs g8rc:$RT), (ins memri34:$D_RA),
- (ins memri34_pcrel:$D_RA), "pld $RT, $D_RA",
- IIC_LdStLFD>;
+ 8LS_DForm_R_SI34_RTA5_p<57, (outs g8rc:$RT), (ins memri34:$D_RA),
+ (ins memri34_pcrel:$D_RA), "pld $RT, $D_RA",
+ IIC_LdStLFD>;
}
let mayStore = 1, mayLoad = 0 in {
defm PSTXV :
- 8LS_DForm_R_D34_XT6_RA5_p<27, (outs), (ins vsrc:$XS, memri34:$D_RA),
- (ins vsrc:$XS, memri34_pcrel:$D_RA),
- "pstxv $XS, $D_RA", IIC_LdStLFD>;
+ 8LS_DForm_R_SI34_XT6_RA5_p<27, (outs), (ins vsrc:$XS, memri34:$D_RA),
+ (ins vsrc:$XS, memri34_pcrel:$D_RA),
+ "pstxv $XS, $D_RA", IIC_LdStLFD>;
defm PSTFS :
- MLS_DForm_R_D34_RTA5_p<52, (outs), (ins f4rc:$FRS, memri34:$D_RA),
- (ins f4rc:$FRS, memri34_pcrel:$D_RA),
- "pstfs $FRS, $D_RA", IIC_LdStLFD>;
+ MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$FRS, memri34:$D_RA),
+ (ins f4rc:$FRS, memri34_pcrel:$D_RA),
+ "pstfs $FRS, $D_RA", IIC_LdStLFD>;
defm PSTFD :
- MLS_DForm_R_D34_RTA5_p<54, (outs), (ins f8rc:$FRS, memri34:$D_RA),
- (ins f8rc:$FRS, memri34_pcrel:$D_RA),
- "pstfd $FRS, $D_RA", IIC_LdStLFD>;
+ MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$FRS, memri34:$D_RA),
+ (ins f8rc:$FRS, memri34_pcrel:$D_RA),
+ "pstfd $FRS, $D_RA", IIC_LdStLFD>;
defm PSTXSSP :
- 8LS_DForm_R_D34_RTA5_p<47, (outs), (ins vfrc:$VRS, memri34:$D_RA),
- (ins vfrc:$VRS, memri34_pcrel:$D_RA),
- "pstxssp $VRS, $D_RA", IIC_LdStLFD>;
+ 8LS_DForm_R_SI34_RTA5_p<47, (outs), (ins vfrc:$VRS, memri34:$D_RA),
+ (ins vfrc:$VRS, memri34_pcrel:$D_RA),
+ "pstxssp $VRS, $D_RA", IIC_LdStLFD>;
defm PSTXSD :
- 8LS_DForm_R_D34_RTA5_p<46, (outs), (ins vfrc:$VRS, memri34:$D_RA),
- (ins vfrc:$VRS, memri34_pcrel:$D_RA),
- "pstxsd $VRS, $D_RA", IIC_LdStLFD>;
+ 8LS_DForm_R_SI34_RTA5_p<46, (outs), (ins vfrc:$VRS, memri34:$D_RA),
+ (ins vfrc:$VRS, memri34_pcrel:$D_RA),
+ "pstxsd $VRS, $D_RA", IIC_LdStLFD>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm PSTB8 :
- MLS_DForm_R_D34_RTA5_p<38, (outs), (ins g8rc:$RS, memri34:$D_RA),
- (ins g8rc:$RS, memri34_pcrel:$D_RA),
- "pstb $RS, $D_RA", IIC_LdStLFD>;
+ MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RS, memri34:$D_RA),
+ (ins g8rc:$RS, memri34_pcrel:$D_RA),
+ "pstb $RS, $D_RA", IIC_LdStLFD>;
defm PSTH8 :
- MLS_DForm_R_D34_RTA5_p<44, (outs), (ins g8rc:$RS, memri34:$D_RA),
- (ins g8rc:$RS, memri34_pcrel:$D_RA),
- "psth $RS, $D_RA", IIC_LdStLFD>;
+ MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RS, memri34:$D_RA),
+ (ins g8rc:$RS, memri34_pcrel:$D_RA),
+ "psth $RS, $D_RA", IIC_LdStLFD>;
defm PSTW8 :
- MLS_DForm_R_D34_RTA5_p<36, (outs), (ins g8rc:$RS, memri34:$D_RA),
- (ins g8rc:$RS, memri34_pcrel:$D_RA),
- "pstw $RS, $D_RA", IIC_LdStLFD>;
+ MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RS, memri34:$D_RA),
+ (ins g8rc:$RS, memri34_pcrel:$D_RA),
+ "pstw $RS, $D_RA", IIC_LdStLFD>;
}
defm PSTB :
- MLS_DForm_R_D34_RTA5_p<38, (outs), (ins gprc:$RS, memri34:$D_RA),
- (ins gprc:$RS, memri34_pcrel:$D_RA),
- "pstb $RS, $D_RA", IIC_LdStLFD>;
+ MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RS, memri34:$D_RA),
+ (ins gprc:$RS, memri34_pcrel:$D_RA),
+ "pstb $RS, $D_RA", IIC_LdStLFD>;
defm PSTH :
- MLS_DForm_R_D34_RTA5_p<44, (outs), (ins gprc:$RS, memri34:$D_RA),
- (ins gprc:$RS, memri34_pcrel:$D_RA),
- "psth $RS, $D_RA", IIC_LdStLFD>;
+ MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RS, memri34:$D_RA),
+ (ins gprc:$RS, memri34_pcrel:$D_RA),
+ "psth $RS, $D_RA", IIC_LdStLFD>;
defm PSTW :
- MLS_DForm_R_D34_RTA5_p<36, (outs), (ins gprc:$RS, memri34:$D_RA),
- (ins gprc:$RS, memri34_pcrel:$D_RA),
- "pstw $RS, $D_RA", IIC_LdStLFD>;
+ MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RS, memri34:$D_RA),
+ (ins gprc:$RS, memri34_pcrel:$D_RA),
+ "pstw $RS, $D_RA", IIC_LdStLFD>;
defm PSTD :
- 8LS_DForm_R_D34_RTA5_p<61, (outs), (ins g8rc:$RS, memri34:$D_RA),
- (ins g8rc:$RS, memri34_pcrel:$D_RA),
- "pstd $RS, $D_RA", IIC_LdStLFD>;
+ 8LS_DForm_R_SI34_RTA5_p<61, (outs), (ins g8rc:$RS, memri34:$D_RA),
+ (ins g8rc:$RS, memri34_pcrel:$D_RA),
+ "pstd $RS, $D_RA", IIC_LdStLFD>;
}
}
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