[PATCH] D75941: [x86][seses] No LFENCEs in basic blocks w/o loads

[Zola Bridges via Phabricator via llvm-commits]

zbrid updated this revision to Diff 250092.
zbrid marked 3 inline comments as done.
zbrid added a comment.

- Update tests to use CHECK-NEXT
- ClangFormat/nits


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75941/new/

https://reviews.llvm.org/D75941

Files:
  llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp
  llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression-omit-lfence-in-bb-without-loads.ll


Index: llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression-omit-lfence-in-bb-without-loads.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression-omit-lfence-in-bb-without-loads.ll
@@ -0,0 +1,31 @@
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -x86-seses-enable -x86-seses-omit-lfence-in-bb-without-loads %s -o - | FileCheck %s --check-prefix=CHECK-FLAGGED
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -x86-seses-enable %s -o - | FileCheck %s --check-prefix=CHECK-FULL
+
+define dso_local void @_Z4buzzv() {
+entry:
+  %a = alloca i32, align 4
+  store i32 10, i32* %a, align 4
+  ret void
+}
+
+; CHECK-FLAGGED: .globl _Z4buzzv                # -- Begin function _Z4buzzv
+; CHECK-FLAGGED-NEXT: .p2align 4, 0x90
+; CHECK-FLAGGED-NEXT: .type _Z4buzzv, at function
+; CHECK-FLAGGED-NEXT:_Z4buzzv:                               # @_Z4buzzv
+; CHECK-FLAGGED-NEXT:.L_Z4buzzv$local:
+; CHECK-FLAGGED-NEXT: .cfi_startproc
+; CHECK-FLAGGED-NEXT:# %bb.0:                                # %entry
+; CHECK-FLAGGED-NEXT: movl $10, -4(%rsp)
+; CHECK-FLAGGED-NEXT: retq
+
+
+; CHECK-FULL: .globl _Z4buzzv                # -- Begin function _Z4buzzv
+; CHECK-FULL-NEXT: .p2align 4, 0x90
+; CHECK-FULL-NEXT: .type _Z4buzzv, at function
+; CHECK-FULL-NEXT:_Z4buzzv:                               # @_Z4buzzv
+; CHECK-FULL-NEXT:.L_Z4buzzv$local:
+; CHECK-FULL-NEXT: .cfi_startproc
+; CHECK-FULL-NEXT:# %bb.0:                                # %entry
+; CHECK-FULL-NEXT: lfence
+; CHECK-FULL-NEXT: movl $10, -4(%rsp)
+; CHECK-FULL-NEXT: retq
Index: llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp
===================================================================
--- llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp
+++ llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp
@@ -50,6 +50,12 @@
                       cl::desc("Omit all lfences before branch instructions."),
                       cl::init(false), cl::Hidden);
 
+static cl::opt<bool> OmitLFENCEInBasicBlocksWithoutLoads(
+    "x86-seses-omit-lfence-in-bb-without-loads",
+    cl::desc("Omit LFENCE in basic blocks without any loads even if there are "
+             "stores."),
+    cl::init(false), cl::Hidden);
+
 static bool hasConstantAddressingMode(const MachineInstr &MI);
 
 namespace {
@@ -81,6 +87,19 @@
   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
   const X86InstrInfo *TII = Subtarget.getInstrInfo();
   for (MachineBasicBlock &MBB : MF) {
+    if (OmitLFENCEInBasicBlocksWithoutLoads) {
+      bool FoundLoad = false;
+      for (const MachineInstr &MI : MBB) {
+        if (MI.mayLoad()) {
+          FoundLoad = true;
+          break;
+        }
+      }
+      if (!FoundLoad) {
+        continue;
+      }
+    }
+
     MachineInstr *FirstTerminator = nullptr;
 
     for (auto &MI : MBB) {


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