[PATCH] D75857: [AMDGPU] Fix using physical registers in vector instructions

Thu Mar 12 11:56:22 PDT 2020

arsenm added a comment.

In D75857#1918810 <https://reviews.llvm.org/D75857#1918810>, @Flakebi wrote:

> In D75857#1917137 <https://reviews.llvm.org/D75857#1917137>, @arsenm wrote:
>
> > I still think theses should not be seeing physical register operands, and it would be better to fix this by avoiding that situation
>
>
> Why is introducing a copy a better fix? And does this mean I should return a COPY when doing `(ballot 1) -> EXEC/EXEC_LO` here? https://reviews.llvm.org/D65088#C1855323NL8643
>
> Wouldn’t a copy use an SGPR and increase the SGPR-count? Then we would generate less optimal code, right?

It should be eliminated later. Introducing physical register constraints earlier is generally bad. I would also worry about earlier passes not expected a non-implicit exec use

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https://reviews.llvm.org/D75857