[PATCH] D75910: [AMDGPU] Improve scheduling model for VOP3b instructions

[Jay Foad via Phabricator via llvm-commits]

foad marked 2 inline comments as done.
foad added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SISchedule.td:32
+// write operand of an instruction that also writes a VGPR result.
+def WriteVCC    : SchedWrite;
+
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rampitec wrote:
> The name suggests it is any VCC write, which is not so. In addition it is not always a VCC. Maybe change to WriteAuxSGPR?
> The name suggests it is any VCC write, which is not so.

Good point. I will try to come up with a better name.

> In addition it is not always a VCC.

True but the name gives you a hint that it is //usually// VCC (i.e. we try to persuade the register allocator to use VCC, and if it does then we can use a smaller instruction encoding).


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Comment at: llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll:1336
+; GFX8-NEXT:    v_readfirstlane_b32 s0, v1
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v4, v3
 ; GFX8-NEXT:    v_mov_b32_e32 v2, s1
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rampitec wrote:
> What about AMDGPUMacroFusion which tries to do exactly the opposite?
Why do you say "the opposite"? Macro fusion tries to put the v_add next to the v_addc (but apparently it fails in this case). My patch should not stop this from working.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D75910/new/

https://reviews.llvm.org/D75910