[PATCH] D75909: [AMDGPU] Remove the gfx10 VALU register destination cache model

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

In D75909#1915333 <https://reviews.llvm.org/D75909#1915333>, @rampitec wrote:

> According to spec "code should be scheduled to reuse data from destination cache whenever possible to reduce RAM reads both for power and performance. The destination cache retires results into the VGPRs at a rate of 1 result per VGPR-bank per cycle."
>
> I.e. from the spec point of view some specific scheduling is needed here even though the impact is small. You may see no impact at all because GCNRegBankReassign fights most of the bank conflicts. It makes sense to remeasure with reassign disabled (-amdgpu-reassign-regs=0). I also think this modeling may be improved, in particular in respect to even and add halves of the cache, but not removed entirely.


If HWRC is modelling a cache for VALU instructions writing VGPRs then why do we use it for non-VALU instructions like:

  def : HWWriteRes<WriteSALU,          [HWSALU,   HWRC], 5>;
  def : HWWriteRes<WriteSMEM,          [HWLGKM,   HWRC], 20>;

?


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  https://reviews.llvm.org/D75909/new/

https://reviews.llvm.org/D75909