[PATCH] D75857: [AMDGPU] Fix using physical registers in vector instructions

[Sebastian Neubauer via Phabricator via llvm-commits]

Flakebi updated this revision to Diff 249133.
Flakebi added a comment.

Remove accidentally added empty line


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75857/new/

https://reviews.llvm.org/D75857

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp


Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4294,13 +4294,22 @@
       continue;
     }
 
-    if (RI.hasAGPRs(MRI.getRegClass(MO.getReg())) &&
-        !isOperandLegal(MI, Idx, &MO)) {
+    bool IsSGPR = false;
+    bool IsAGPR = false;
+    if (MO.getReg().isVirtual()) {
+      IsAGPR = RI.hasAGPRs(MRI.getRegClass(MO.getReg()));
+      IsSGPR = RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
+    } else {
+      IsAGPR = RI.isAGPR(MRI, MO.getReg());
+      IsAGPR = RI.isSGPRReg(MRI, MO.getReg());
+    }
+
+    if (IsAGPR && !isOperandLegal(MI, Idx, &MO)) {
       legalizeOpWithMove(MI, Idx);
       continue;
     }
 
-    if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
+    if (!IsSGPR)
       continue; // VGPRs are legal
 
     // We can use one SGPR in each VOP3 instruction prior to GFX10
@@ -5929,9 +5938,14 @@
 
     // If this could be a VGPR or an SGPR, Check the dynamic register class.
     Register Reg = MO.getReg();
-    const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
-    if (RI.isSGPRClass(RegRC))
-      UsedSGPRs[i] = Reg;
+    if (Reg.isVirtual()) {
+      const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
+      if (RI.isSGPRClass(RegRC))
+        UsedSGPRs[i] = Reg;
+    } else {
+      if (RI.isSGPRReg(MRI, Reg))
+        UsedSGPRs[i] = Reg;
+    }
   }
 
   // We don't have a required SGPR operand, so we have a bit more freedom in


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