[PATCH] D75812: Implement PUL.PS and PUU.PS instructions

Simon Atanasyan via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Mar 8 05:50:58 PDT 2020


atanasyan requested changes to this revision.
atanasyan added a comment.
This revision now requires changes to proceed.

The following test cases failed on my machine. Initially, assembler shows `error: unknown instruction`. Now assembler shows correct error message `instruction requires a CPU feature not currently enabled` and the checks should be updated and moved to `invalid-xxx.s` files.

  MC/Mips/mips1/invalid-mips5-wrong-error.s
  MC/Mips/mips2/invalid-mips5-wrong-error.s
  MC/Mips/mips3/invalid-mips5-wrong-error.s
  MC/Mips/mips4/invalid-mips5-wrong-error.s
  MC/Mips/mips64r6/invalid-mips5-wrong-error.s


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75812/new/

https://reviews.llvm.org/D75812





More information about the llvm-commits mailing list