[PATCH] D75751: [AArch64][SVE] Implement structured load intrinsics

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, efriedma, rengolin.
Herald added subscribers: danielkiss, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a project: LLVM.

This patch adds initial support for the following instrinsics:

- llvm.aarch64.sve.ld2
- llvm.aarch64.sve.ld3
- llvm.aarch64.sve.ld4

For loading two, three and four vectors worth of data. Basic codegen for
reg+immediate forms are implemented. Reg+reg addressing modes will be
addressed in a later patch.

The types returned by these intrinsics have a number of elements that is
a multiple of the elements in a 128-bit vector for a given type and N
where N is the number of vectors being loaded, i.e. 2, 3 or 4. Thus, for
32-bit elements the types are:

  LD2 : <n x 8 x i32>
  LD3 : <n x 12 x i32>
  LD4 : <n x 16 x i32>

This is implemented with target-specific intrinsics for each variant
that take the same operands as the IR intrinsic but return N values,
where the type of each value is a full vector, i.e. <n x 4 x i32> in the
above example. These values are then concatenated using the standard
concat_vector intrinsic to maintain type legality with the IR. Values
are subsequently extracted using the vector tuple extract intrinsic
'llvm.aarch64.sve.tuple.get' implemented in D75674 <https://reviews.llvm.org/D75674>, which looks through
the concat_vectors and allows us to handle otherwise illegal types. All
of this is handled in SelectionDAGBuilder such that SelectionDAG can
rely on standard mechanisms to break down concat_vector for these
irregular (not necessarily a power-of-two) values.

These types cannot currently be passed between basic blocks as
copy-to-reg/copy-from-reg support isn't implemented. Given this
limitation these intrinsics must be immediately followed by an extract,
using the intrinsic mentioned above. Calling convention support does
exist however (added in D75674 <https://reviews.llvm.org/D75674>) so these types can be passed to/from
function calls. We mark the vector tuple intrinsics as reading memory to
prevent moves between BBs.

These intrinsics are intended for use in the Arm C Language
Extension (ACLE).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D75751

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/sve-intrinsics-loads-with-extract.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll

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