[PATCH] D75601: [AArch64][SVE] Add intrinsics for non-temporal scatters/gathers

[Andrzej Warzynski via Phabricator via llvm-commits]

andwar marked 2 inline comments as done.
andwar added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5265
     // TLI.getShiftAmount().
-    assert(N2.getValueSizeInBits() >= Log2_32_Ceil(N1.getValueSizeInBits()) &&
-           "Invalid use of small shift amount with oversized value!");
+    assert(N2.getValueType().getScalarSizeInBits().getFixedSize() >=
+       Log2_32_Ceil(VT.getScalarSizeInBits().getFixedSize()) &&
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This change is needed to accommodate for scalable types.


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Comment at: llvm/test/CodeGen/AArch64/sve2-intrinsics-nt-gather-loads-64bit-scaled-offset.ll:12
+; CHECK-LABEL: gldnt1h_index
+; CHECK:          mul z0.d, z0.d, #2
+; CHECK-NEXT:     ldnt1h  { z0.d }, p0/z, [z0.d, x0]
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efriedma wrote:
> andwar wrote:
> > efriedma wrote:
> > > "mul"?  Can we make a shift instead?
> > Sadly there are no patterns for `lsl` yet, so I'd have to add a call to `@llvm.aarch64.sve.lsl` for this to wok. It's an option, but I'd prefer to leave a  TODO instead (e.g. `// TODO Replace MUL with SHL once patterns for lsl are added)`.
> The lsl patterns are pretty simple; see https://reviews.llvm.org/D73602 .  But sure, we can leave that for later.
Fair point, updated.

Btw, thanks for the link, but it seems unrelated. Did you have some other patch in mind?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D75601/new/

https://reviews.llvm.org/D75601